dds.map.eqn

使用DDS技术

-- Copyright (C) 1991-2005 Altera Corporation
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-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- applicable agreement for further details.
--F1_q[0] is fsk_decode:u7|q[0]
--operation mode is arithmetic

F1_q[0]_lut_out = !F1_q[0];
F1_q[0] = DFFEAS(F1_q[0]_lut_out, CLK, VCC, , , , , , );

--F1L91 is fsk_decode:u7|q[0]~106
--operation mode is arithmetic

F1L91 = CARRY(F1_q[0]);


--F1_q[1] is fsk_decode:u7|q[1]
--operation mode is arithmetic

F1_q[1]_carry_eqn = F1L91;
F1_q[1]_lut_out = F1_q[1] $ (F1_q[1]_carry_eqn);
F1_q[1] = DFFEAS(F1_q[1]_lut_out, CLK, VCC, , , , , , );

--F1L12 is fsk_decode:u7|q[1]~110
--operation mode is arithmetic

F1L12 = CARRY(!F1L91 # !F1_q[1]);


--F1_q[2] is fsk_decode:u7|q[2]
--operation mode is arithmetic

F1_q[2]_carry_eqn = F1L12;
F1_q[2]_lut_out = F1_q[2] $ (!F1_q[2]_carry_eqn);
F1_q[2] = DFFEAS(F1_q[2]_lut_out, CLK, VCC, , , , , , );

--F1L32 is fsk_decode:u7|q[2]~114
--operation mode is arithmetic

F1L32 = CARRY(F1_q[2] & (!F1L12));


--F1_q[3] is fsk_decode:u7|q[3]
--operation mode is arithmetic

F1_q[3]_carry_eqn = F1L32;
F1_q[3]_lut_out = F1_q[3] $ (F1_q[3]_carry_eqn);
F1_q[3] = DFFEAS(F1_q[3]_lut_out, CLK, VCC, , , , , , );

--F1L52 is fsk_decode:u7|q[3]~118
--operation mode is arithmetic

F1L52 = CARRY(!F1L32 # !F1_q[3]);


--F1_q[4] is fsk_decode:u7|q[4]
--operation mode is arithmetic

F1_q[4]_carry_eqn = F1L52;
F1_q[4]_lut_out = F1_q[4] $ (!F1_q[4]_carry_eqn);
F1_q[4] = DFFEAS(F1_q[4]_lut_out, CLK, VCC, , , , , , );

--F1L72 is fsk_decode:u7|q[4]~122
--operation mode is arithmetic

F1L72 = CARRY(F1_q[4] & (!F1L52));


--F1_q[5] is fsk_decode:u7|q[5]
--operation mode is arithmetic

F1_q[5]_carry_eqn = F1L72;
F1_q[5]_lut_out = F1_q[5] $ (F1_q[5]_carry_eqn);
F1_q[5] = DFFEAS(F1_q[5]_lut_out, CLK, VCC, , , , , , );

--F1L92 is fsk_decode:u7|q[5]~126
--operation mode is arithmetic

F1L92 = CARRY(!F1L72 # !F1_q[5]);


--F1_q[6] is fsk_decode:u7|q[6]
--operation mode is arithmetic

F1_q[6]_carry_eqn = F1L92;
F1_q[6]_lut_out = F1_q[6] $ (!F1_q[6]_carry_eqn);
F1_q[6] = DFFEAS(F1_q[6]_lut_out, CLK, VCC, , , , , , );

--F1L13 is fsk_decode:u7|q[6]~130
--operation mode is arithmetic

F1L13 = CARRY(F1_q[6] & (!F1L92));


--F1_q[7] is fsk_decode:u7|q[7]
--operation mode is normal

F1_q[7]_carry_eqn = F1L13;
F1_q[7]_lut_out = F1_q[7] $ (F1_q[7]_carry_eqn);
F1_q[7] = DFFEAS(F1_q[7]_lut_out, CLK, VCC, , , , , , );


--H1_q_a[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
H1_q_a[0]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[0]_PORT_A_address_reg = DFFE(H1_q_a[0]_PORT_A_address, H1_q_a[0]_clock_0, , , );
H1_q_a[0]_clock_0 = CLK;
H1_q_a[0]_PORT_A_data_out = MEMORY(, , H1_q_a[0]_PORT_A_address_reg, , , , , , H1_q_a[0]_clock_0, , , , , );
H1_q_a[0]_PORT_A_data_out_reg = DFFE(H1_q_a[0]_PORT_A_data_out, H1_q_a[0]_clock_0, , , );
H1_q_a[0] = H1_q_a[0]_PORT_A_data_out_reg[0];


--H1_q_a[1] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
H1_q_a[1]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[1]_PORT_A_address_reg = DFFE(H1_q_a[1]_PORT_A_address, H1_q_a[1]_clock_0, , , );
H1_q_a[1]_clock_0 = CLK;
H1_q_a[1]_PORT_A_data_out = MEMORY(, , H1_q_a[1]_PORT_A_address_reg, , , , , , H1_q_a[1]_clock_0, , , , , );
H1_q_a[1]_PORT_A_data_out_reg = DFFE(H1_q_a[1]_PORT_A_data_out, H1_q_a[1]_clock_0, , , );
H1_q_a[1] = H1_q_a[1]_PORT_A_data_out_reg[0];


--H1_q_a[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
H1_q_a[2]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[2]_PORT_A_address_reg = DFFE(H1_q_a[2]_PORT_A_address, H1_q_a[2]_clock_0, , , );
H1_q_a[2]_clock_0 = CLK;
H1_q_a[2]_PORT_A_data_out = MEMORY(, , H1_q_a[2]_PORT_A_address_reg, , , , , , H1_q_a[2]_clock_0, , , , , );
H1_q_a[2]_PORT_A_data_out_reg = DFFE(H1_q_a[2]_PORT_A_data_out, H1_q_a[2]_clock_0, , , );
H1_q_a[2] = H1_q_a[2]_PORT_A_data_out_reg[0];


--H1_q_a[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
H1_q_a[3]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[3]_PORT_A_address_reg = DFFE(H1_q_a[3]_PORT_A_address, H1_q_a[3]_clock_0, , , );
H1_q_a[3]_clock_0 = CLK;
H1_q_a[3]_PORT_A_data_out = MEMORY(, , H1_q_a[3]_PORT_A_address_reg, , , , , , H1_q_a[3]_clock_0, , , , , );
H1_q_a[3]_PORT_A_data_out_reg = DFFE(H1_q_a[3]_PORT_A_data_out, H1_q_a[3]_clock_0, , , );
H1_q_a[3] = H1_q_a[3]_PORT_A_data_out_reg[0];


--H1_q_a[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
H1_q_a[4]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[4]_PORT_A_address_reg = DFFE(H1_q_a[4]_PORT_A_address, H1_q_a[4]_clock_0, , , );
H1_q_a[4]_clock_0 = CLK;
H1_q_a[4]_PORT_A_data_out = MEMORY(, , H1_q_a[4]_PORT_A_address_reg, , , , , , H1_q_a[4]_clock_0, , , , , );
H1_q_a[4]_PORT_A_data_out_reg = DFFE(H1_q_a[4]_PORT_A_data_out, H1_q_a[4]_clock_0, , , );
H1_q_a[4] = H1_q_a[4]_PORT_A_data_out_reg[0];


--H1_q_a[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
H1_q_a[5]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[5]_PORT_A_address_reg = DFFE(H1_q_a[5]_PORT_A_address, H1_q_a[5]_clock_0, , , );
H1_q_a[5]_clock_0 = CLK;
H1_q_a[5]_PORT_A_data_out = MEMORY(, , H1_q_a[5]_PORT_A_address_reg, , , , , , H1_q_a[5]_clock_0, , , , , );
H1_q_a[5]_PORT_A_data_out_reg = DFFE(H1_q_a[5]_PORT_A_data_out, H1_q_a[5]_clock_0, , , );
H1_q_a[5] = H1_q_a[5]_PORT_A_data_out_reg[0];


--H1_q_a[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
H1_q_a[6]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[6]_PORT_A_address_reg = DFFE(H1_q_a[6]_PORT_A_address, H1_q_a[6]_clock_0, , , );
H1_q_a[6]_clock_0 = CLK;
H1_q_a[6]_PORT_A_data_out = MEMORY(, , H1_q_a[6]_PORT_A_address_reg, , , , , , H1_q_a[6]_clock_0, , , , , );
H1_q_a[6]_PORT_A_data_out_reg = DFFE(H1_q_a[6]_PORT_A_data_out, H1_q_a[6]_clock_0, , , );
H1_q_a[6] = H1_q_a[6]_PORT_A_data_out_reg[0];


--H1_q_a[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
H1_q_a[7]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_clock_0 = CLK;
H1_q_a[7]_PORT_A_data_out = MEMORY(, , H1_q_a[7]_PORT_A_address_reg, , , , , , H1_q_a[7]_clock_0, , , , , );
H1_q_a[7]_PORT_A_data_out_reg = DFFE(H1_q_a[7]_PORT_A_data_out, H1_q_a[7]_clock_0, , , );
H1_q_a[7] = H1_q_a[7]_PORT_A_data_out_reg[0];


--F1_s is fsk_decode:u7|s
--operation mode is normal

F1_s_lut_out = F1_m[4] # !F1L1 & F1_m[2] & F1_m[3];
F1_s = DFFEAS(F1_s_lut_out, !F1_q[7], VCC, , , , , , );


--C2_DOUT[0] is REG7B:u5|DOUT[0]
--operation mode is normal

C2_DOUT[0]_lut_out = C1_DOUT[0];
C2_DOUT[0] = DFFEAS(C2_DOUT[0]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[1] is REG7B:u5|DOUT[1]
--operation mode is normal

C2_DOUT[1]_lut_out = C1_DOUT[1];
C2_DOUT[1] = DFFEAS(C2_DOUT[1]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[2] is REG7B:u5|DOUT[2]
--operation mode is normal

C2_DOUT[2]_lut_out = C1_DOUT[2];
C2_DOUT[2] = DFFEAS(C2_DOUT[2]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[3] is REG7B:u5|DOUT[3]
--operation mode is normal

C2_DOUT[3]_lut_out = C1_DOUT[3];
C2_DOUT[3] = DFFEAS(C2_DOUT[3]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[4] is REG7B:u5|DOUT[4]
--operation mode is normal

C2_DOUT[4]_lut_out = C1_DOUT[4];
C2_DOUT[4] = DFFEAS(C2_DOUT[4]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[5] is REG7B:u5|DOUT[5]
--operation mode is normal

C2_DOUT[5]_lut_out = C1_DOUT[5];
C2_DOUT[5] = DFFEAS(C2_DOUT[5]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[6] is REG7B:u5|DOUT[6]
--operation mode is normal

C2_DOUT[6]_lut_out = C1_DOUT[6];
C2_DOUT[6] = DFFEAS(C2_DOUT[6]_lut_out, CLK, VCC, , , , , , );


--F1_m[0] is fsk_decode:u7|m[0]
--operation mode is arithmetic

F1_m[0]_lut_out = F1L61 $ !F1_m[0];
F1_m[0] = DFFEAS(F1_m[0]_lut_out, CLK, VCC, , , , , F1L3, );

--F1L6 is fsk_decode:u7|m[0]~78
--operation mode is arithmetic

F1L6 = CARRY(!F1L61 & F1_m[0]);


--F1_m[1] is fsk_decode:u7|m[1]
--operation mode is arithmetic

F1_m[1]_carry_eqn = F1L6;
F1_m[1]_lut_out = F1_m[1] $ (F1_m[1]_carry_eqn);
F1_m[1] = DFFEAS(F1_m[1]_lut_out, CLK, VCC, , , , , F1L3, );

--F1L8 is fsk_decode:u7|m[1]~82
--operation mode is arithmetic

F1L8 = CARRY(!F1L6 # !F1_m[1]);


--F1L1 is fsk_decode:u7|LessThan~313
--operation mode is normal

F1L1 = !F1_m[0] & !F1_m[1];


--F1_m[2] is fsk_decode:u7|m[2]
--operation mode is arithmetic

F1_m[2]_carry_eqn = F1L8;
F1_m[2]_lut_out = F1_m[2] $ (!F1_m[2]_carry_eqn);
F1_m[2] = DFFEAS(F1_m[2]_lut_out, CLK, VCC, , , , , F1L3, );

--F1L01 is fsk_decode:u7|m[2]~86
--operation mode is arithmetic

F1L01 = CARRY(F1_m[2] & (!F1L8));


--F1_m[3] is fsk_decode:u7|m[3]
--operation mode is arithmetic

F1_m[3]_carry_eqn = F1L01;
F1_m[3]_lut_out = F1_m[3] $ (F1_m[3]_carry_eqn);
F1_m[3] = DFFEAS(F1_m[3]_lut_out, CLK, VCC, , , , , F1L3, );

--F1L21 is fsk_decode:u7|m[3]~90
--operation mode is arithmetic

F1L21 = CARRY(!F1L01 # !F1_m[3]);


--F1_m[4] is fsk_decode:u7|m[4]
--operation mode is normal

F1_m[4]_carry_eqn = F1L21;