dds.tan.rpt
来自「使用DDS技术」· RPT 代码 · 共 224 行 · 第 1/5 页
RPT
224 行
; N/A ; 178.54 MHz ( period = 5.601 ns ) ; fsk_decode:u7|reg[2] ; fsk_decode:u7|m[0] ; CLK ; CLK ; None ; None ; 5.399 ns ;
; N/A ; 188.50 MHz ( period = 5.305 ns ) ; fsk_decode:u7|reg[7] ; fsk_decode:u7|m[0] ; CLK ; CLK ; None ; None ; 5.103 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg1 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg2 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg3 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg4 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg5 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg6 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg1 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg2 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg3 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg4 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg5 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg6 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg1 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg2 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg3 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg4 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg5 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg6 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg1 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg2 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg3 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg4 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg5 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg6 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg1 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg2 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg3 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg4 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg5 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg6 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg1 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg2 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg3 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg4 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg5 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg6 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[2] ; CLK ; CLK ; None ; None ; 4.319 ns ;
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