dds.map.rpt

使用DDS技术

; Assignment     ; Value ; From ; To   ;
+----------------+-------+------+------+
; POWER_UP_LEVEL ; Low   ; -    ; m[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; m[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; m[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; m[3] ;
; POWER_UP_LEVEL ; Low   ; -    ; m[4] ;
; POWER_UP_LEVEL ; Low   ; -    ; q[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; q[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; q[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; q[3] ;
; POWER_UP_LEVEL ; Low   ; -    ; q[4] ;
; POWER_UP_LEVEL ; Low   ; -    ; q[5] ;
; POWER_UP_LEVEL ; Low   ; -    ; q[6] ;
; POWER_UP_LEVEL ; Low   ; -    ; q[7] ;
+----------------+-------+------+------+


+-----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sin_rom:u3|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+----------------------------------+
; Parameter Name                     ; Value           ; Type                             ;
+------------------------------------+-----------------+----------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                          ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                       ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                     ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                     ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                   ;
; OPERATION_MODE                     ; ROM             ; Untyped                          ;
; WIDTH_A                            ; 8               ; Integer                          ;
; WIDTHAD_A                          ; 7               ; Integer                          ;
; NUMWORDS_A                         ; 128             ; Integer                          ;
; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                          ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                          ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                          ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                          ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                          ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                          ;
; WIDTH_B                            ; 1               ; Untyped                          ;
; WIDTHAD_B                          ; 1               ; Untyped                          ;
; NUMWORDS_B                         ; 1               ; Untyped                          ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                          ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                          ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                          ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                          ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                          ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                          ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                          ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                          ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                          ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                          ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                          ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                          ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                          ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                          ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                          ;
; BYTE_SIZE                          ; 8               ; Untyped                          ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                          ;
; INIT_FILE                          ; sin7.mif        ; Untyped                          ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                          ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                          ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                          ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                          ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                          ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                          ;
; DEVICE_FAMILY                      ; Cyclone         ; Untyped                          ;
; CBXI_PARAMETER                     ; altsyncram_hq21 ; Untyped                          ;
+------------------------------------+-----------------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Jun 25 10:38:02 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds
Info: Found 2 design units, including 1 entities, in source file fsk_decode.vhd
    Info: Found design unit 1: fsk_decode-behave
    Info: Found entity 1: fsk_decode
Info: Found 2 design units, including 1 entities, in source file DDS.VHD
    Info: Found design unit 1: DDS-one
    Info: Found entity 1: DDS
Info: Found 2 design units, including 1 entities, in source file SIN_ROM.VHD
    Info: Found design unit 1: sin_rom-SYN
    Info: Found entity 1: sin_rom
Info: Found 2 design units, including 1 entities, in source file ps7.vhd
    Info: Found design unit 1: ps7-behav
    Info: Found entity 1: ps7
Info: Found 2 design units, including 1 entities, in source file adder7b.vhd
    Info: Found design unit 1: ADDER7B-behav
    Info: Found entity 1: ADDER7B
Info: Found 2 design units, including 1 entities, in source file reg7b.vhd
    Info: Found design unit 1: REG7B-behav
    Info: Found entity 1: REG7B
Info: Elaborating entity "DDS" for the top level hierarchy
Info: Elaborating entity "ADDER7B" for hierarchy "ADDER7B:u1"
Info: Elaborating entity "REG7B" for hierarchy "REG7B:u2"
Info: Elaborating entity "sin_rom" for hierarchy "sin_rom:u3"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "sin_rom:u3|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "sin_rom:u3|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hq21.tdf
    Info: Found entity 1: altsyncram_hq21
Info: Elaborating entity "altsyncram_hq21" for hierarchy "sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated"
Info: Elaborating entity "ps7" for hierarchy "ps7:u6"
Warning (10492): VHDL Process Statement warning at ps7.vhd(27): signal "c3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "fsk_decode" for hierarchy "fsk_decode:u7"
Info: Duplicate registers merged to single register
    Info: Duplicate register "ps7:u6|count[0]" merged to single register "fsk_decode:u7|q[0]"
    Info: Duplicate register "ps7:u6|count[1]" merged to single register "fsk_decode:u7|q[1]"
    Info: Duplicate register "ps7:u6|count[2]" merged to single register "fsk_decode:u7|q[2]"
    Info: Duplicate register "ps7:u6|count[3]" merged to single register "fsk_decode:u7|q[3]"
    Info: Duplicate register "ps7:u6|count[4]" merged to single register "fsk_decode:u7|q[4]"
    Info: Duplicate register "ps7:u6|count[5]" merged to single register "fsk_decode:u7|q[5]"
    Info: Duplicate register "ps7:u6|count[6]" merged to single register "fsk_decode:u7|q[6]"
    Info: Duplicate register "ps7:u6|count[7]" merged to single register "fsk_decode:u7|q[7]"
Info: Registers with preset signals will power-up high
Info: Implemented 75 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 17 output pins
    Info: Implemented 48 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Jun 25 10:38:17 2007
    Info: Elapsed time: 00:00:16