dds.vhd

使用DDS技术

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS                                     -- 顶层设计
    PORT (     CLK : IN  STD_LOGIC;          
               count1:out std_logic_vector(7 downto 0);
               dds1:out std_logic_vector(7 downto 0);
               dc_out:out std_logic;
               ls:in std_logic);        --解调后接收到的码
     END;
ARCHITECTURE one OF DDS IS
    COMPONENT REG7B    --32位寄存器
        PORT (  LOAD : IN STD_LOGIC;
                 DIN : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
                DOUT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );
    END COMPONENT;
    COMPONENT ADDER7B                 --7位加法器
       PORT (  A : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
               B : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
               S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)     );
    END COMPONENT;
   
    COMPONENT SIN_ROM
      PORT	( address	: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
		      clock	: IN STD_LOGIC ;
	            	q	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)	);
    END COMPONENT; 
    component ps7 is
port(clk:in std_logic;
load:in std_logic;
q:out std_logic;
count1:out std_logic_vector(7 downto 0));
end component;
    component fsk_decode
       PORT (     CLK : IN  STD_LOGIC;
            receive  : in STD_LOGIC_VECTOR(7 DOWNTO 0) ;
             s:out std_logic);
    END  component;
     signal   din:  std_logic;   
     SIGNAL F7B   : STD_LOGIC_VECTOR(6 DOWNTO 0);--输入的7位的频率字，作为累加值
     SIGNAL D7B   : STD_LOGIC_VECTOR(6 DOWNTO 0);--7位的地址信号，7位寄存器的输出
     SIGNAL DIN7B : STD_LOGIC_VECTOR(6 DOWNTO 0);--7位的地址信号，7位寄存器的输入
     SIGNAL P7B   : STD_LOGIC_VECTOR( 6 DOWNTO 0);     --7位相位字信号,恒为零
     SIGNAL LIN7B : STD_LOGIC_VECTOR( 6 DOWNTO 0);    --输入到寄存器的地址信号
     SIGNAL SIN7B : STD_LOGIC_VECTOR( 6 DOWNTO 0);   --寄存器输出的地址信号  
     signal dds_out : STD_LOGIC_VECTOR(7 DOWNTO 0);  --发送的已调波信号
 BEGIN 
 F7B(6 DOWNTO 0)<=(2=>din,0=>(not din),others=>'0'); 
 P7B(6 DOWNTO 0)<=(others=>'0');
 u1 : ADDER7B  PORT MAP( A=>F7B,B=>D7B, S=>DIN7B );
 u2 :   REG7B  PORT MAP( DOUT=>D7B,DIN=> DIN7B, LOAD=>CLK );
 u3 :  SIN_ROM  PORT MAP( address=>SIN7B, q=>dds_out, clock=>CLK ); --产生已调的正弦波
 u4 : ADDER7B  PORT MAP( A=>P7B,B=>D7B,S=>LIN7B );
 u5 :   REG7B  PORT MAP( DOUT=>SIN7B,DIN=>LIN7B, LOAD=>CLK );
 u6: ps7   port  map(clk=>clk,load=>ls,q=>din,count1=>count1);
dds1<=dds_out;
u7:fsk_decode port map(clk=>clk,receive=>dds_out,s=>dc_out); --解调程序模块
END;