dds.map.eqn

利用VHDL语言实现在

D1L5 = CARRY(!D1L3 # !D1_q[2]);


--D1_q[3] is PL_DPSK2:u2|q[3]
--operation mode is arithmetic

D1_q[3]_carry_eqn = D1L5;
D1_q[3]_lut_out = D1_q[3] $ (!D1_q[3]_carry_eqn);
D1_q[3] = DFFEAS(D1_q[3]_lut_out, CLK, VCC, , , ~GND, , , D1L61);

--D1L7 is PL_DPSK2:u2|q[3]~229
--operation mode is arithmetic

D1L7 = CARRY(D1_q[3] & (!D1L5));


--D1_q[4] is PL_DPSK2:u2|q[4]
--operation mode is arithmetic

D1_q[4]_carry_eqn = D1L7;
D1_q[4]_lut_out = D1_q[4] $ (D1_q[4]_carry_eqn);
D1_q[4] = DFFEAS(D1_q[4]_lut_out, CLK, VCC, , , ~GND, , , D1L61);

--D1L9 is PL_DPSK2:u2|q[4]~233
--operation mode is arithmetic

D1L9 = CARRY(!D1L7 # !D1_q[4]);


--D1L02 is PL_DPSK2:u2|reduce_nor~42
--operation mode is normal

D1L02 = !D1_q[1] & !D1_q[2] & !D1_q[3] & !D1_q[4];


--D1_q[5] is PL_DPSK2:u2|q[5]
--operation mode is arithmetic

D1_q[5]_carry_eqn = D1L9;
D1_q[5]_lut_out = D1_q[5] $ (!D1_q[5]_carry_eqn);
D1_q[5] = DFFEAS(D1_q[5]_lut_out, CLK, VCC, , , ~GND, , , D1L61);

--D1L11 is PL_DPSK2:u2|q[5]~237
--operation mode is arithmetic

D1L11 = CARRY(D1_q[5] & (!D1L9));


--D1_q[6] is PL_DPSK2:u2|q[6]
--operation mode is arithmetic

D1_q[6]_carry_eqn = D1L11;
D1_q[6]_lut_out = D1_q[6] $ (D1_q[6]_carry_eqn);
D1_q[6] = DFFEAS(D1_q[6]_lut_out, CLK, VCC, , , ~GND, , , D1L61);

--D1L31 is PL_DPSK2:u2|q[6]~241
--operation mode is arithmetic

D1L31 = CARRY(!D1L11 # !D1_q[6]);


--D1_q[7] is PL_DPSK2:u2|q[7]
--operation mode is arithmetic

D1_q[7]_carry_eqn = D1L31;
D1_q[7]_lut_out = D1_q[7] $ (!D1_q[7]_carry_eqn);
D1_q[7] = DFFEAS(D1_q[7]_lut_out, CLK, VCC, , , ~GND, , , D1L61);

--D1L51 is PL_DPSK2:u2|q[7]~245
--operation mode is arithmetic

D1L51 = CARRY(D1_q[7] & (!D1L31));


--D1_q[8] is PL_DPSK2:u2|q[8]
--operation mode is normal

D1_q[8]_carry_eqn = D1L51;
D1_q[8]_lut_out = D1_q[8] $ (D1_q[8]_carry_eqn);
D1_q[8] = DFFEAS(D1_q[8]_lut_out, CLK, VCC, , , ~GND, , , D1L61);


--D1L12 is PL_DPSK2:u2|reduce_nor~43
--operation mode is normal

D1L12 = !D1_q[5] & !D1_q[6] & !D1_q[7] & !D1_q[8];


--D1L91 is PL_DPSK2:u2|reduce_nor~1
--operation mode is normal

D1L91 = C1_q[0] & D1L02 & D1L12;


--B1_c3 is ps7:u0|c3
--operation mode is normal

B1_c3_lut_out = !B1_c2;
B1_c3 = DFFEAS(B1_c3_lut_out, !C1_q[8], !ls, , , , , , );


--C1_P7B[6] is DDS1:u1|P7B[6]
--operation mode is normal

C1_P7B[6]_lut_out = !C1_P7B[6];
C1_P7B[6] = DFFEAS(C1_P7B[6]_lut_out, C1_q[8], VCC, , B1_q, , , , );


--E1_y is fangbo:u3|y
--operation mode is normal

E1_y_lut_out = K1_q_a[7];
E1_y = DFFEAS(E1_y_lut_out, CLK, VCC, , E1L5, , , , );


--D1L81 is PL_DPSK2:u2|reduce_nor~0
--operation mode is normal

D1L81 = C1_q[0] # !D1L12 # !D1L02;


--D1L61 is PL_DPSK2:u2|q[7]~252
--operation mode is normal

D1L61 = D1L02 & D1L12;


--B1_c2 is ps7:u0|c2
--operation mode is normal

B1_c2_lut_out = B1_c1;
B1_c2 = DFFEAS(B1_c2_lut_out, !C1_q[8], !ls, , , , , , );


--E1_fout2[7] is fangbo:u3|fout2[7]
--operation mode is normal

E1_fout2[7]_lut_out = E1_fout1[7];
E1_fout2[7] = DFFEAS(E1_fout2[7]_lut_out, CLK, VCC, , , , , , );


--E1_fout1[7] is fangbo:u3|fout1[7]
--operation mode is normal

E1_fout1[7]_lut_out = K1_q_a[7];
E1_fout1[7] = DFFEAS(E1_fout1[7]_lut_out, CLK, VCC, , , , , , );


--E1L5 is fangbo:u3|process0~2
--operation mode is normal

E1L5 = K1_q_a[7] & E1_fout2[7] & E1_fout1[7] # !K1_q_a[7] & !E1_fout2[7] & !E1_fout1[7];


--B1_c1 is ps7:u0|c1
--operation mode is normal

B1_c1_lut_out = !B1_c0;
B1_c1 = DFFEAS(B1_c1_lut_out, !C1_q[8], !ls, , , , , , );


--B1_c0 is ps7:u0|c0
--operation mode is normal

B1_c0_lut_out = !B1_c0;
B1_c0 = DFFEAS(B1_c0_lut_out, !C1_q[8], !ls, , !B1_c3, , , , );


--~GND is ~GND
--operation mode is normal

~GND = GND;


--CLK is CLK
--operation mode is input

CLK = INPUT();


--ls is ls
--operation mode is input

ls = INPUT();


--dds_out[0] is dds_out[0]
--operation mode is output

dds_out[0] = OUTPUT(K1_q_a[0]);


--dds_out[1] is dds_out[1]
--operation mode is output

dds_out[1] = OUTPUT(K1_q_a[1]);


--dds_out[2] is dds_out[2]
--operation mode is output

dds_out[2] = OUTPUT(K1_q_a[2]);


--dds_out[3] is dds_out[3]
--operation mode is output

dds_out[3] = OUTPUT(K1_q_a[3]);


--dds_out[4] is dds_out[4]
--operation mode is output

dds_out[4] = OUTPUT(K1_q_a[4]);


--dds_out[5] is dds_out[5]
--operation mode is output

dds_out[5] = OUTPUT(K1_q_a[5]);


--dds_out[6] is dds_out[6]
--operation mode is output

dds_out[6] = OUTPUT(K1_q_a[6]);


--dds_out[7] is dds_out[7]
--operation mode is output

dds_out[7] = OUTPUT(K1_q_a[7]);


--dc_out is dc_out
--operation mode is output

dc_out = OUTPUT(D1_y);


--count1[0] is count1[0]
--operation mode is output

count1[0] = OUTPUT(C1_q[0]);


--count1[1] is count1[1]
--operation mode is output

count1[1] = OUTPUT(C1_q[1]);


--count1[2] is count1[2]
--operation mode is output

count1[2] = OUTPUT(C1_q[2]);


--count1[3] is count1[3]
--operation mode is output

count1[3] = OUTPUT(C1_q[3]);


--count1[4] is count1[4]
--operation mode is output

count1[4] = OUTPUT(C1_q[4]);


--count1[5] is count1[5]
--operation mode is output

count1[5] = OUTPUT(C1_q[5]);


--count1[6] is count1[6]
--operation mode is output

count1[6] = OUTPUT(C1_q[6]);


--count1[7] is count1[7]
--operation mode is output

count1[7] = OUTPUT(C1_q[7]);


--count1[8] is count1[8]
--operation mode is output

count1[8] = OUTPUT(C1_q[8]);


--din1 is din1
--operation mode is output

din1 = OUTPUT(B1_q);


--C1L6 is DDS1:u1|q[0]~113
--operation mode is normal

C1L6 = !C1_q[0];


--B1L5 is ps7:u0|c3~3
--operation mode is normal

B1L5 = !B1_c3;