📄 dds.sim.rpt
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; |DDS|DDS1:u1|q[2] ; |DDS|DDS1:u1|q[2]~42 ; cout0 ;
; |DDS|DDS1:u1|q[2] ; |DDS|DDS1:u1|q[2]~42COUT1_52 ; cout1 ;
; |DDS|DDS1:u1|q[3] ; |DDS|DDS1:u1|q[3]~43 ; cout0 ;
; |DDS|DDS1:u1|q[3] ; |DDS|DDS1:u1|q[3]~43COUT1_53 ; cout1 ;
; |DDS|DDS1:u1|q[4] ; |DDS|DDS1:u1|q[4]~44 ; cout0 ;
; |DDS|DDS1:u1|q[4] ; |DDS|DDS1:u1|q[4]~44COUT1 ; cout1 ;
; |DDS|DDS1:u1|q[5] ; |DDS|DDS1:u1|q[5]~45 ; cout ;
; |DDS|DDS1:u1|q[6] ; |DDS|DDS1:u1|q[6]~46COUT1_54 ; cout1 ;
; |DDS|DDS1:u1|q[7] ; |DDS|DDS1:u1|q[7]~47COUT1_55 ; cout1 ;
; |DDS|ps7:u0|q ; |DDS|ps7:u0|q ; regout ;
; |DDS|DDS1:u1|REG7B:u5|DOUT[2] ; |DDS|DDS1:u1|REG7B:u5|DOUT[2] ; regout ;
; |DDS|DDS1:u1|REG7B:u5|DOUT[3] ; |DDS|DDS1:u1|REG7B:u5|DOUT[3] ; regout ;
; |DDS|DDS1:u1|REG7B:u5|DOUT[4] ; |DDS|DDS1:u1|REG7B:u5|DOUT[4] ; regout ;
; |DDS|DDS1:u1|REG7B:u5|DOUT[5] ; |DDS|DDS1:u1|REG7B:u5|DOUT[5] ; regout ;
; |DDS|DDS1:u1|REG7B:u5|DOUT[6] ; |DDS|DDS1:u1|REG7B:u5|DOUT[6] ; regout ;
; |DDS|PL_DPSK2:u2|q[1] ; |DDS|PL_DPSK2:u2|q[1]~165 ; cout0 ;
; |DDS|PL_DPSK2:u2|q[1] ; |DDS|PL_DPSK2:u2|q[1]~165COUT1_175 ; cout1 ;
; |DDS|PL_DPSK2:u2|q[2] ; |DDS|PL_DPSK2:u2|q[2]~166 ; cout0 ;
; |DDS|PL_DPSK2:u2|q[2] ; |DDS|PL_DPSK2:u2|q[2]~166COUT1_176 ; cout1 ;
; |DDS|PL_DPSK2:u2|q[3] ; |DDS|PL_DPSK2:u2|q[3]~167 ; cout0 ;
; |DDS|PL_DPSK2:u2|q[3] ; |DDS|PL_DPSK2:u2|q[3]~167COUT1_177 ; cout1 ;
; |DDS|PL_DPSK2:u2|q[4] ; |DDS|PL_DPSK2:u2|q[4]~168 ; cout0 ;
; |DDS|PL_DPSK2:u2|q[4] ; |DDS|PL_DPSK2:u2|q[4]~168COUT1 ; cout1 ;
; |DDS|PL_DPSK2:u2|Equal1~67 ; |DDS|PL_DPSK2:u2|Equal1~67 ; combout ;
; |DDS|PL_DPSK2:u2|q[5] ; |DDS|PL_DPSK2:u2|q[5]~169 ; cout ;
; |DDS|PL_DPSK2:u2|q[6] ; |DDS|PL_DPSK2:u2|q[6]~170COUT1_178 ; cout1 ;
; |DDS|PL_DPSK2:u2|q[7] ; |DDS|PL_DPSK2:u2|q[7]~171COUT1_179 ; cout1 ;
; |DDS|PL_DPSK2:u2|Equal1~68 ; |DDS|PL_DPSK2:u2|Equal1~68 ; combout ;
; |DDS|PL_DPSK2:u2|Equal1~69 ; |DDS|PL_DPSK2:u2|Equal1~69 ; combout ;
; |DDS|PL_DPSK2:u2|xx2 ; |DDS|PL_DPSK2:u2|xx2 ; regout ;
; |DDS|PL_DPSK2:u2|xx1 ; |DDS|PL_DPSK2:u2|xx1 ; regout ;
; |DDS|ps7:u0|c3 ; |DDS|ps7:u0|c3 ; regout ;
; |DDS|DDS1:u1|P7B[6] ; |DDS|DDS1:u1|P7B[6] ; regout ;
; |DDS|PL_DPSK2:u2|Equal0~20 ; |DDS|PL_DPSK2:u2|Equal0~20 ; combout ;
; |DDS|PL_DPSK2:u2|q[1]~173 ; |DDS|PL_DPSK2:u2|q[1]~173 ; combout ;
; |DDS|fangbo:u3|yy ; |DDS|fangbo:u3|yy ; regout ;
; |DDS|ps7:u0|c2 ; |DDS|ps7:u0|c2 ; regout ;
; |DDS|fangbo:u3|fout1[7] ; |DDS|fangbo:u3|fout1[7] ; regout ;
; |DDS|fangbo:u3|fout2[7] ; |DDS|fangbo:u3|fout2[7] ; regout ;
; |DDS|ps7:u0|c1 ; |DDS|ps7:u0|c1 ; regout ;
; |DDS|ps7:u0|c0 ; |DDS|ps7:u0|c0 ; regout ;
; |DDS|CLK ; |DDS|CLK ; combout ;
; |DDS|dds_out[0] ; |DDS|dds_out[0] ; padio ;
; |DDS|dds_out[1] ; |DDS|dds_out[1] ; padio ;
; |DDS|dds_out[2] ; |DDS|dds_out[2] ; padio ;
; |DDS|dds_out[3] ; |DDS|dds_out[3] ; padio ;
; |DDS|dds_out[4] ; |DDS|dds_out[4] ; padio ;
; |DDS|dds_out[5] ; |DDS|dds_out[5] ; padio ;
; |DDS|dds_out[6] ; |DDS|dds_out[6] ; padio ;
; |DDS|dds_out[7] ; |DDS|dds_out[7] ; padio ;
; |DDS|dc_out ; |DDS|dc_out ; padio ;
; |DDS|count1[0] ; |DDS|count1[0] ; padio ;
; |DDS|count1[1] ; |DDS|count1[1] ; padio ;
; |DDS|count1[2] ; |DDS|count1[2] ; padio ;
; |DDS|count1[3] ; |DDS|count1[3] ; padio ;
; |DDS|count1[4] ; |DDS|count1[4] ; padio ;
; |DDS|count1[5] ; |DDS|count1[5] ; padio ;
; |DDS|count1[6] ; |DDS|count1[6] ; padio ;
; |DDS|count1[7] ; |DDS|count1[7] ; padio ;
; |DDS|count1[8] ; |DDS|count1[8] ; padio ;
; |DDS|din1 ; |DDS|din1 ; padio ;
; |DDS|DDS1:u1|q[0]~$wirecell ; |DDS|DDS1:u1|q[0]~$wirecell ; combout ;
; |DDS|PL_DPSK2:u2|Equal0~20$wirecell ; |DDS|PL_DPSK2:u2|Equal0~20$wirecell ; combout ;
; |DDS|ps7:u0|c3~$wirecell ; |DDS|ps7:u0|c3~$wirecell ; combout ;
+-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+-----------------------+---------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------------------+---------------------------+------------------+
; |DDS|DDS1:u1|q[6] ; |DDS|DDS1:u1|q[6]~46 ; cout0 ;
; |DDS|DDS1:u1|q[7] ; |DDS|DDS1:u1|q[7]~47 ; cout0 ;
; |DDS|PL_DPSK2:u2|q[6] ; |DDS|PL_DPSK2:u2|q[6]~170 ; cout0 ;
; |DDS|PL_DPSK2:u2|q[7] ; |DDS|PL_DPSK2:u2|q[7]~171 ; cout0 ;
; |DDS|~GND ; |DDS|~GND ; combout ;
; |DDS|ls ; |DDS|ls ; combout ;
+-----------------------+---------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+-----------------------+---------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------------------+---------------------------+------------------+
; |DDS|DDS1:u1|q[6] ; |DDS|DDS1:u1|q[6]~46 ; cout0 ;
; |DDS|DDS1:u1|q[7] ; |DDS|DDS1:u1|q[7]~47 ; cout0 ;
; |DDS|PL_DPSK2:u2|q[6] ; |DDS|PL_DPSK2:u2|q[6]~170 ; cout0 ;
; |DDS|PL_DPSK2:u2|q[7] ; |DDS|PL_DPSK2:u2|q[7]~171 ; cout0 ;
; |DDS|~GND ; |DDS|~GND ; combout ;
+-----------------------+---------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
Info: Processing started: Mon Jun 25 10:42:50 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off DDS -c dds
Warning: Ignored node in vector source file. Can't find corresponding node name "fangbo:u3|y" in design.
Info: Inverted registers were found during simulation
Info: Register: |DDS|ps7:u0|c3
Info: Register: |DDS|ps7:u0|c0
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 92.50 %
Info: Number of transitions in simulation is 187853
Info: Vector file dds.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 1 warning
Info: Processing ended: Mon Jun 25 10:43:11 2007
Info: Elapsed time: 00:00:22
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