system.map.qmsg

对saa7113缓存的逻辑控制单元实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 24 17:06:54 2008 " "Info: Processing started: Thu Apr 24 17:06:54 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SYSTEM -c SYSTEM " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SYSTEM -c SYSTEM" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../count191/counter19.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../count191/counter19.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter19-rtl " "Info: Found design unit 1: counter19-rtl" {  } { { "../count191/counter19.vhd" "" { Text "F:/count191/counter19.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter19 " "Info: Found entity 1: counter19" {  } { { "../count191/counter19.vhd" "" { Text "F:/count191/counter19.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lock_19/lock_19.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lock_19/lock_19.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lock_19-one " "Info: Found design unit 1: lock_19-one" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lock_19 " "Info: Found entity 1: lock_19" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div2/div2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div2/div2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div2-one " "Info: Found design unit 1: div2-one" {  } { { "div2/div2.vhd" "" { Text "F:/system/div2/div2.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div2 " "Info: Found entity 1: div2" {  } { { "div2/div2.vhd" "" { Text "F:/system/div2/div2.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lock_19/SYSTEM.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file lock_19/SYSTEM.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 SYSTEM " "Info: Found entity 1: SYSTEM" {  } { { "lock_19/SYSTEM.bdf" "" { Schematic "F:/system/lock_19/SYSTEM.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "SYSTEM " "Info: Elaborating entity \"SYSTEM\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div2 div2:inst1 " "Info: Elaborating entity \"div2\" for hierarchy \"div2:inst1\"" {  } { { "lock_19/SYSTEM.bdf" "inst1" { Schematic "F:/system/lock_19/SYSTEM.bdf" { { 160 192 304 256 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter19 counter19:inst6 " "Info: Elaborating entity \"counter19\" for hierarchy \"counter19:inst6\"" {  } { { "lock_19/SYSTEM.bdf" "inst6" { Schematic "F:/system/lock_19/SYSTEM.bdf" { { 16 440 568 112 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lock_19 lock_19:inst3 " "Info: Elaborating entity \"lock_19\" for hierarchy \"lock_19:inst3\"" {  } { { "lock_19/SYSTEM.bdf" "inst3" { Schematic "F:/system/lock_19/SYSTEM.bdf" { { 176 656 848 272 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "addr_out lock_19.vhd(11) " "Warning (10631): VHDL Process Statement warning at lock_19.vhd(11): inferring latch(es) for signal or variable \"addr_out\", which holds its previous value in one or more paths through the process" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[0\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[0\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[1\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[1\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[2\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[2\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[3\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[3\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[4\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[4\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[5\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[5\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[6\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[6\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[7\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[7\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[8\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[8\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[9\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[9\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[10\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[10\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[11\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[11\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[12\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[12\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[13\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[13\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[14\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[14\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[15\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[15\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[16\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[16\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr_out\[17\] lock_19.vhd(11) " "Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for \"addr_out\[17\]\"" {  } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}