📄 system.tan.qmsg
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{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "lock_19:inst2\|addr_out\[0\]~154 " "Warning: Node \"lock_19:inst2\|addr_out\[0\]~154\"" { } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0} } { { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 -1 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "VREF " "Info: Assuming node \"VREF\" is an undefined clock" { } { { "lock_19/SYSTEM.bdf" "" { Schematic "F:/system/lock_19/SYSTEM.bdf" { { 136 -24 144 152 "VREF" "" } } } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "VREF" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "HREF " "Info: Assuming node \"HREF\" is an undefined clock" { } { { "lock_19/SYSTEM.bdf" "" { Schematic "F:/system/lock_19/SYSTEM.bdf" { { 96 -24 144 112 "HREF" "" } } } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "HREF" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "LCC " "Info: Assuming node \"LCC\" is an undefined clock" { } { { "lock_19/SYSTEM.bdf" "" { Schematic "F:/system/lock_19/SYSTEM.bdf" { { 40 -24 144 56 "LCC" "" } } } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCC" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "VREF register counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\] register counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"VREF\" has Internal fmax of 76.92 MHz between source register \"counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\]\" and destination register \"counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\] 1 REG LC23 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC23; Fanout = 21; REG Node = 'counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\] 2 REG LC26 20 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC26; Fanout = 20; REG Node = 'counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 75.00 % ) " "Info: Total cell delay = 6.000 ns ( 75.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 25.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VREF destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock \"VREF\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns VREF 1 CLK PIN_87 21 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'VREF'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { VREF } "NODE_NAME" } } { "lock_19/SYSTEM.bdf" "" { Schematic "F:/system/lock_19/SYSTEM.bdf" { { 136 -24 144 152 "VREF" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\] 2 REG LC26 20 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC26; Fanout = 20; REG Node = 'counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { VREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns ( 90.00 % ) " "Info: Total cell delay = 9.000 ns ( 90.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.00 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { VREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { VREF VREF~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VREF source 10.000 ns - Longest register " "Info: - Longest clock path from clock \"VREF\" to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns VREF 1 CLK PIN_87 21 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'VREF'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { VREF } "NODE_NAME" } } { "lock_19/SYSTEM.bdf" "" { Schematic "F:/system/lock_19/SYSTEM.bdf" { { 136 -24 144 152 "VREF" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\] 2 REG LC23 21 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC23; Fanout = 21; REG Node = 'counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { VREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns ( 90.00 % ) " "Info: Total cell delay = 9.000 ns ( 90.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.00 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { VREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { VREF VREF~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { VREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { VREF VREF~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { VREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { VREF VREF~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { VREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { VREF VREF~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { VREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { VREF VREF~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "HREF register counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\] register counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"HREF\" has Internal fmax of 76.92 MHz between source register \"counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\]\" and destination register \"counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\] 1 REG LC23 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC23; Fanout = 21; REG Node = 'counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\] 2 REG LC26 20 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC26; Fanout = 20; REG Node = 'counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 75.00 % ) " "Info: Total cell delay = 6.000 ns ( 75.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 25.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "HREF destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock \"HREF\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns HREF 1 CLK PIN_92 20 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_92; Fanout = 20; CLK Node = 'HREF'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { HREF } "NODE_NAME" } } { "lock_19/SYSTEM.bdf" "" { Schematic "F:/system/lock_19/SYSTEM.bdf" { { 96 -24 144 112 "HREF" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\] 2 REG LC26 20 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC26; Fanout = 20; REG Node = 'counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { HREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { HREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { HREF HREF~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "HREF source 10.000 ns - Longest register " "Info: - Longest clock path from clock \"HREF\" to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns HREF 1 CLK PIN_92 20 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_92; Fanout = 20; CLK Node = 'HREF'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { HREF } "NODE_NAME" } } { "lock_19/SYSTEM.bdf" "" { Schematic "F:/system/lock_19/SYSTEM.bdf" { { 96 -24 144 112 "HREF" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\] 2 REG LC23 21 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC23; Fanout = 21; REG Node = 'counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { HREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { HREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { HREF HREF~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { HREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { HREF HREF~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { HREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { HREF HREF~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { HREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { HREF HREF~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { HREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { HREF HREF~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "LCC register counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\] register counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"LCC\" has Internal fmax of 76.92 MHz between source register \"counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\]\" and destination register \"counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\] 1 REG LC23 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC23; Fanout = 21; REG Node = 'counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\] 2 REG LC26 20 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC26; Fanout = 20; REG Node = 'counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 75.00 % ) " "Info: Total cell delay = 6.000 ns ( 75.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 25.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCC destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock \"LCC\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns LCC 1 CLK PIN_85 20 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_85; Fanout = 20; CLK Node = 'LCC'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCC } "NODE_NAME" } } { "lock_19/SYSTEM.bdf" "" { Schematic "F:/system/lock_19/SYSTEM.bdf" { { 40 -24 144 56 "LCC" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\] 2 REG LC26 20 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC26; Fanout = 20; REG Node = 'counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[3\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { LCC counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { LCC counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { LCC LCC~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCC source 10.000 ns - Longest register " "Info: - Longest clock path from clock \"LCC\" to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns LCC 1 CLK PIN_85 20 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_85; Fanout = 20; CLK Node = 'LCC'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCC } "NODE_NAME" } } { "lock_19/SYSTEM.bdf" "" { Schematic "F:/system/lock_19/SYSTEM.bdf" { { 40 -24 144 56 "LCC" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\] 2 REG LC23 21 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC23; Fanout = 21; REG Node = 'counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[2\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { LCC counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { LCC counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { LCC LCC~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { LCC counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { LCC LCC~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { LCC counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { LCC LCC~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { LCC counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { LCC LCC~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[3] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { LCC counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { LCC LCC~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "HREF ODD_ADD\[18\] counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[18\] 24.000 ns register " "Info: tco from clock \"HREF\" to destination pin \"ODD_ADD\[18\]\" through register \"counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[18\]\" is 24.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "HREF source 10.000 ns + Longest register " "Info: + Longest clock path from clock \"HREF\" to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns HREF 1 CLK PIN_92 20 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_92; Fanout = 20; CLK Node = 'HREF'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { HREF } "NODE_NAME" } } { "lock_19/SYSTEM.bdf" "" { Schematic "F:/system/lock_19/SYSTEM.bdf" { { 96 -24 144 112 "HREF" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[18\] 2 REG LC12 5 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC12; Fanout = 5; REG Node = 'counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[18\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { HREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[18] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { HREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[18] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { HREF HREF~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[18] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[18\] 1 REG LC12 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC12; Fanout = 5; REG Node = 'counter19:inst6\|lpm_counter:count_signal_rtl_0\|dffs\[18\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[18] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 282 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(9.000 ns) 9.000 ns lock_19:inst2\|addr_out\[18\]~226 2 COMB LOOP LC9 3 " "Info: 2: + IC(0.000 ns) + CELL(9.000 ns) = 9.000 ns; Loc. = LC9; Fanout = 3; COMB LOOP Node = 'lock_19:inst2\|addr_out\[18\]~226'" { { "Info" "ITDB_PART_OF_SCC" "lock_19:inst2\|addr_out\[18\]~226 LC9 " "Info: Loc. = LC9; Node \"lock_19:inst2\|addr_out\[18\]~226\"" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { lock_19:inst2|addr_out[18]~226 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { lock_19:inst2|addr_out[18]~226 } "NODE_NAME" } } { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 -1 0 } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[18] lock_19:inst2|addr_out[18]~226 } "NODE_NAME" } } { "lock_19/lock_19.vhd" "" { Text "F:/system/lock_19/lock_19.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns ODD_ADD\[18\] 3 PIN PIN_97 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_97; Fanout = 0; PIN Node = 'ODD_ADD\[18\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { lock_19:inst2|addr_out[18]~226 ODD_ADD[18] } "NODE_NAME" } } { "lock_19/SYSTEM.bdf" "" { Schematic "F:/system/lock_19/SYSTEM.bdf" { { 56 904 1080 72 "ODD_ADD\[18..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns ( 100.00 % ) " "Info: Total cell delay = 13.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[18] lock_19:inst2|addr_out[18]~226 ODD_ADD[18] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[18] lock_19:inst2|addr_out[18]~226 ODD_ADD[18] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 9.000ns 4.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { HREF counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[18] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { HREF HREF~out counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[18] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[18] lock_19:inst2|addr_out[18]~226 ODD_ADD[18] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { counter19:inst6|lpm_counter:count_signal_rtl_0|dffs[18] lock_19:inst2|addr_out[18]~226 ODD_ADD[18] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 9.000ns 4.000ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 40 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 40 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "97 " "Info: Allocated 97 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 24 17:07:13 2008 " "Info: Processing ended: Thu Apr 24 17:07:13 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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