📄 lock_19.map.rpt
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Analysis & Synthesis report for lock_19
Thu Apr 24 11:29:34 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. User-Specified and Inferred Latches
8. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Apr 24 11:29:34 2008 ;
; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name ; lock_19 ;
; Top-level Entity Name ; lock_19 ;
; Family ; MAX7000S ;
; Total macrocells ; 19 ;
; Total pins ; 39 ;
+-----------------------------+-----------------------------------------+
+---------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+------------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+------------------+---------------+
; Device ; EPM7128STC100-15 ; ;
; Top-level entity name ; lock_19 ; lock_19 ;
; Family name ; MAX7000S ; Stratix ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Use smart compilation ; Off ; Off ;
+----------------------------------------------------------------------+------------------+---------------+
+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; lock_19.vhd ; yes ; User VHDL File ; F:/lock_19/lock_19.vhd ;
+----------------------------------+-----------------+-----------------+------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 19 ;
; Total registers ; 0 ;
; I/O pins ; 39 ;
; Maximum fan-out node ; lock ;
; Maximum fan-out ; 19 ;
; Total fan-out ; 76 ;
; Average fan-out ; 1.31 ;
+----------------------+----------------------+
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |lock_19 ; 19 ; 39 ; |lock_19 ;
+----------------------------+------------+------+---------------------+
+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; addr_out[0]$latch ; lock ; yes ;
; addr_out[1]$latch ; lock ; yes ;
; addr_out[2]$latch ; lock ; yes ;
; addr_out[3]$latch ; lock ; yes ;
; addr_out[4]$latch ; lock ; yes ;
; addr_out[5]$latch ; lock ; yes ;
; addr_out[6]$latch ; lock ; yes ;
; addr_out[7]$latch ; lock ; yes ;
; addr_out[8]$latch ; lock ; yes ;
; addr_out[9]$latch ; lock ; yes ;
; addr_out[10]$latch ; lock ; yes ;
; addr_out[11]$latch ; lock ; yes ;
; addr_out[12]$latch ; lock ; yes ;
; addr_out[13]$latch ; lock ; yes ;
; addr_out[14]$latch ; lock ; yes ;
; addr_out[15]$latch ; lock ; yes ;
; addr_out[16]$latch ; lock ; yes ;
; addr_out[17]$latch ; lock ; yes ;
; addr_out[18]$latch ; lock ; yes ;
; Number of user-specified and inferred latches = 19 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Thu Apr 24 11:29:33 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lock_19 -c lock_19
Info: Found 2 design units, including 1 entities, in source file lock_19.vhd
Info: Found design unit 1: lock_19-one
Info: Found entity 1: lock_19
Info: Elaborating entity "lock_19" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at lock_19.vhd(11): inferring latch(es) for signal or variable "addr_out", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[0]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[1]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[2]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[3]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[4]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[5]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[6]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[7]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[8]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[9]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[10]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[11]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[12]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[13]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[14]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[15]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[16]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[17]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[18]"
Info: Implemented 58 device resources after synthesis - the final resource count might be different
Info: Implemented 20 input pins
Info: Implemented 19 output pins
Info: Implemented 19 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Allocated 132 megabytes of memory during processing
Info: Processing ended: Thu Apr 24 11:29:34 2008
Info: Elapsed time: 00:00:01
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