📄 system.map.rpt
字号:
; lock_19:inst2|addr_out[5] ; div2:inst1|q ; yes ;
; lock_19:inst2|addr_out[4] ; div2:inst1|q ; yes ;
; lock_19:inst2|addr_out[3] ; div2:inst1|q ; yes ;
; lock_19:inst2|addr_out[2] ; div2:inst1|q ; yes ;
; lock_19:inst2|addr_out[1] ; div2:inst1|q ; yes ;
; lock_19:inst2|addr_out[0] ; div2:inst1|q ; yes ;
; Number of user-specified and inferred latches = 19 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+-------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------+--------------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------+--------------------------------------+
; inst7/count_signal[1] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[0] ; Stuck at GND due to stuck port clear ;
; inst7/cout ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[2] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[3] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[4] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[5] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[6] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[7] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[8] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[9] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[10] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[11] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[12] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[13] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[14] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[15] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[16] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[17] ; Stuck at GND due to stuck port clear ;
; inst7/count_signal[18] ; Stuck at GND due to stuck port clear ;
; Total Number of Removed Registers = 20 ; ;
+----------------------------------------+--------------------------------------+
+-------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: counter19:inst6|lpm_counter:count_signal_rtl_0 ;
+------------------------+-------------------+----------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+----------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 19 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Thu Apr 24 17:06:54 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SYSTEM -c SYSTEM
Info: Found 2 design units, including 1 entities, in source file ../count191/counter19.vhd
Info: Found design unit 1: counter19-rtl
Info: Found entity 1: counter19
Info: Found 2 design units, including 1 entities, in source file lock_19/lock_19.vhd
Info: Found design unit 1: lock_19-one
Info: Found entity 1: lock_19
Info: Found 2 design units, including 1 entities, in source file div2/div2.vhd
Info: Found design unit 1: div2-one
Info: Found entity 1: div2
Info: Found 1 design units, including 1 entities, in source file lock_19/SYSTEM.bdf
Info: Found entity 1: SYSTEM
Info: Elaborating entity "SYSTEM" for the top level hierarchy
Info: Elaborating entity "div2" for hierarchy "div2:inst1"
Info: Elaborating entity "counter19" for hierarchy "counter19:inst6"
Info: Elaborating entity "lock_19" for hierarchy "lock_19:inst3"
Warning (10631): VHDL Process Statement warning at lock_19.vhd(11): inferring latch(es) for signal or variable "addr_out", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[0]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[1]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[2]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[3]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[4]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[5]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[6]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[7]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[8]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[9]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[10]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[11]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[12]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[13]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[14]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[15]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[16]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[17]"
Info (10041): Verilog HDL or VHDL info at lock_19.vhd(11): inferred latch for "addr_out[18]"
Warning: Reduced register "counter19:inst7|count_signal[1]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[0]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|cout" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[2]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[3]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[4]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[5]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[6]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[7]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[8]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[9]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[10]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[11]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[12]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[13]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[14]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[15]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[16]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[17]" with stuck clear port to stuck value GND
Warning: Reduced register "counter19:inst7|count_signal[18]" with stuck clear port to stuck value GND
Info: Inferred 1 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=19) from the following logic: "counter19:inst6|count_signal[0]~19"
Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "counter19:inst6|lpm_counter:count_signal_rtl_0"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "EVN_ful" stuck at GND
Warning: Pin "EVN_ADD[18]" stuck at GND
Warning: Pin "EVN_ADD[17]" stuck at GND
Warning: Pin "EVN_ADD[16]" stuck at GND
Warning: Pin "EVN_ADD[15]" stuck at GND
Warning: Pin "EVN_ADD[14]" stuck at GND
Warning: Pin "EVN_ADD[13]" stuck at GND
Warning: Pin "EVN_ADD[12]" stuck at GND
Warning: Pin "EVN_ADD[11]" stuck at GND
Warning: Pin "EVN_ADD[10]" stuck at GND
Warning: Pin "EVN_ADD[9]" stuck at GND
Warning: Pin "EVN_ADD[8]" stuck at GND
Warning: Pin "EVN_ADD[7]" stuck at GND
Warning: Pin "EVN_ADD[6]" stuck at GND
Warning: Pin "EVN_ADD[5]" stuck at GND
Warning: Pin "EVN_ADD[4]" stuck at GND
Warning: Pin "EVN_ADD[3]" stuck at GND
Warning: Pin "EVN_ADD[2]" stuck at GND
Warning: Pin "EVN_ADD[1]" stuck at GND
Warning: Pin "EVN_ADD[0]" stuck at GND
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin "VREF" to global clock signal
Info: Implemented 106 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 42 output pins
Info: Implemented 61 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 42 warnings
Info: Allocated 135 megabytes of memory during processing
Info: Processing ended: Thu Apr 24 17:06:58 2008
Info: Elapsed time: 00:00:04
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -