count19_a.tan.rpt

对saa7113缓存的逻辑控制单元实现

; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:lpm_counter_component|dffs[9]  ; lpm_counter:lpm_counter_component|dffs[18] ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:lpm_counter_component|dffs[10] ; lpm_counter:lpm_counter_component|dffs[18] ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:lpm_counter_component|dffs[11] ; lpm_counter:lpm_counter_component|dffs[18] ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:lpm_counter_component|dffs[12] ; lpm_counter:lpm_counter_component|dffs[18] ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:lpm_counter_component|dffs[13] ; lpm_counter:lpm_counter_component|dffs[18] ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:lpm_counter_component|dffs[14] ; lpm_counter:lpm_counter_component|dffs[18] ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:lpm_counter_component|dffs[15] ; lpm_counter:lpm_counter_component|dffs[18] ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:lpm_counter_component|dffs[16] ; lpm_counter:lpm_counter_component|dffs[18] ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:lpm_counter_component|dffs[17] ; lpm_counter:lpm_counter_component|dffs[18] ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:lpm_counter_component|dffs[18] ; lpm_counter:lpm_counter_component|dffs[18] ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
+-------+----------------------------------+--------------------------------------------+--------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------------------------+
; tco                                                                                                 ;
+-------+--------------+------------+--------------------------------------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From                                       ; To    ; From Clock ;
+-------+--------------+------------+--------------------------------------------+-------+------------+
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[18] ; q[18] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[17] ; q[17] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[16] ; q[16] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[15] ; q[15] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[14] ; q[14] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[13] ; q[13] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[12] ; q[12] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[11] ; q[11] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[10] ; q[10] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[9]  ; q[9]  ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[8]  ; q[8]  ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[7]  ; q[7]  ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[6]  ; q[6]  ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[5]  ; q[5]  ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[4]  ; q[4]  ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[3]  ; q[3]  ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[2]  ; q[2]  ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[1]  ; q[1]  ; clock      ;
; N/A   ; None         ; 8.000 ns   ; lpm_counter:lpm_counter_component|dffs[0]  ; q[0]  ; clock      ;
+-------+--------------+------------+--------------------------------------------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Apr 24 16:28:35 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off count19_a -c count19_a
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 76.92 MHz between source register "lpm_counter:lpm_counter_component|dffs[0]" and destination register "lpm_counter:lpm_counter_component|dffs[0]" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 20; REG Node = 'lpm_counter:lpm_counter_component|dffs[0]'
        Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC17; Fanout = 20; REG Node = 'lpm_counter:lpm_counter_component|dffs[0]'
        Info: Total cell delay = 8.000 ns ( 100.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clock" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_87; Fanout = 19; CLK Node = 'clock'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC17; Fanout = 20; REG Node = 'lpm_counter:lpm_counter_component|dffs[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clock" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_87; Fanout = 19; CLK Node = 'clock'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC17; Fanout = 20; REG Node = 'lpm_counter:lpm_counter_component|dffs[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock "clock" to destination pin "q[18]" through register "lpm_counter:lpm_counter_component|dffs[18]" is 8.000 ns
    Info: + Longest clock path from clock "clock" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_87; Fanout = 19; CLK Node = 'clock'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC16; Fanout = 2; REG Node = 'lpm_counter:lpm_counter_component|dffs[18]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 2; REG Node = 'lpm_counter:lpm_counter_component|dffs[18]'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 'q[18]'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 97 megabytes of memory during processing
    Info: Processing ended: Thu Apr 24 16:28:37 2008
    Info: Elapsed time: 00:00:02