clkscan2.map.qmsg

来自「采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启」· QMSG 代码 · 共 49 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 14 21:22:45 2008 " "Info: Processing started: Mon Apr 14 21:22:45 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clkscan2 -c clkscan2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clkscan2 -c clkscan2" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "button.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file button.v" { { "Info" "ISGN_ENTITY_NAME" "1 button " "Info: Found entity 1: button" {  } { { "button.v" "" { Text "e:/clk_scan/clkscan2/button.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "p7segment.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file p7segment.v" { { "Info" "ISGN_ENTITY_NAME" "1 p7segment " "Info: Found entity 1: p7segment" {  } { { "p7segment.v" "" { Text "e:/clk_scan/clkscan2/p7segment.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkdiv1ms.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkdiv1ms.v" { { "Info" "ISGN_ENTITY_NAME" "1 clkdiv1ms " "Info: Found entity 1: clkdiv1ms" {  } { { "clkdiv1ms.v" "" { Text "e:/clk_scan/clkscan2/clkdiv1ms.v" 2 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkdiv.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkdiv.v" { { "Info" "ISGN_ENTITY_NAME" "1 clkdiv " "Info: Found entity 1: clkdiv" {  } { { "clkdiv.v" "" { Text "e:/clk_scan/clkscan2/clkdiv.v" 2 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkscan.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkscan.v" { { "Info" "ISGN_ENTITY_NAME" "1 clkscan " "Info: Found entity 1: clkscan" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 11 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkscan2.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkscan2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 clkscan2 " "Info: Found entity 1: clkscan2" {  } { { "clkscan2.bdf" "" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clkscan2 " "Info: Elaborating entity \"clkscan2\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "p7segment p7segment:inst7 " "Info: Elaborating entity \"p7segment\" for hierarchy \"p7segment:inst7\"" {  } { { "clkscan2.bdf" "inst7" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { { 144 392 544 240 "inst7" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clkscan clkscan:inst6 " "Info: Elaborating entity \"clkscan\" for hierarchy \"clkscan:inst6\"" {  } { { "clkscan2.bdf" "inst6" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { { 0 384 528 96 "inst6" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkscan.v(23) " "Warning: Verilog HDL assignment warning at clkscan.v(23): truncated value with size 32 to match size of target (1)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkscan.v(25) " "Warning: Verilog HDL assignment warning at clkscan.v(25): truncated value with size 32 to match size of target (1)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 25 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(34) " "Warning: Verilog HDL assignment warning at clkscan.v(34): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clkscan.v(35) " "Warning: Verilog HDL assignment warning at clkscan.v(35): truncated value with size 32 to match size of target (4)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(42) " "Warning: Verilog HDL assignment warning at clkscan.v(42): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 42 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(43) " "Warning: Verilog HDL assignment warning at clkscan.v(43): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 43 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(44) " "Warning: Verilog HDL assignment warning at clkscan.v(44): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 44 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(45) " "Warning: Verilog HDL assignment warning at clkscan.v(45): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 45 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(46) " "Warning: Verilog HDL assignment warning at clkscan.v(46): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 46 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(47) " "Warning: Verilog HDL assignment warning at clkscan.v(47): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 47 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(48) " "Warning: Verilog HDL assignment warning at clkscan.v(48): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(49) " "Warning: Verilog HDL assignment warning at clkscan.v(49): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(50) " "Warning: Verilog HDL assignment warning at clkscan.v(50): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 50 0 0 } }  } 0}