clkscan2.map.qmsg

来自「采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启」· QMSG 代码 · 共 49 行 · 第 1/2 页

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clkscan.v(54) " "Warning: Verilog HDL assignment warning at clkscan.v(54): truncated value with size 32 to match size of target (4)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 54 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clkscan.v(56) " "Warning: Verilog HDL assignment warning at clkscan.v(56): truncated value with size 32 to match size of target (4)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 56 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(58) " "Warning: Verilog HDL assignment warning at clkscan.v(58): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 58 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clkdiv clkdiv:inst " "Info: Elaborating entity \"clkdiv\" for hierarchy \"clkdiv:inst\"" {  } { { "clkscan2.bdf" "inst" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { { 0 208 304 96 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkdiv.v(10) " "Warning: Verilog HDL assignment warning at clkdiv.v(10): truncated value with size 32 to match size of target (1)" {  } { { "clkdiv.v" "" { Text "e:/clk_scan/clkscan2/clkdiv.v" 10 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clkdiv.v(12) " "Warning: Verilog HDL assignment warning at clkdiv.v(12): truncated value with size 32 to match size of target (23)" {  } { { "clkdiv.v" "" { Text "e:/clk_scan/clkscan2/clkdiv.v" 12 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clkdiv.v(14) " "Warning: Verilog HDL assignment warning at clkdiv.v(14): truncated value with size 32 to match size of target (23)" {  } { { "clkdiv.v" "" { Text "e:/clk_scan/clkscan2/clkdiv.v" 14 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "button button:inst2 " "Info: Elaborating entity \"button\" for hierarchy \"button:inst2\"" {  } { { "clkscan2.bdf" "inst2" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { { 224 208 312 296 "inst2" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 button.v(11) " "Warning: Verilog HDL assignment warning at button.v(11): truncated value with size 32 to match size of target (7)" {  } { { "button.v" "" { Text "e:/clk_scan/clkscan2/button.v" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 button.v(13) " "Warning: Verilog HDL assignment warning at button.v(13): truncated value with size 32 to match size of target (7)" {  } { { "button.v" "" { Text "e:/clk_scan/clkscan2/button.v" 13 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clkdiv1ms clkdiv1ms:inst3 " "Info: Elaborating entity \"clkdiv1ms\" for hierarchy \"clkdiv1ms:inst3\"" {  } { { "clkscan2.bdf" "inst3" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { { 104 208 304 200 "inst3" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkdiv1ms.v(10) " "Warning: Verilog HDL assignment warning at clkdiv1ms.v(10): truncated value with size 32 to match size of target (1)" {  } { { "clkdiv1ms.v" "" { Text "e:/clk_scan/clkscan2/clkdiv1ms.v" 10 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 15 clkdiv1ms.v(12) " "Warning: Verilog HDL assignment warning at clkdiv1ms.v(12): truncated value with size 32 to match size of target (15)" {  } { { "clkdiv1ms.v" "" { Text "e:/clk_scan/clkscan2/clkdiv1ms.v" 12 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 15 clkdiv1ms.v(14) " "Warning: Verilog HDL assignment warning at clkdiv1ms.v(14): truncated value with size 32 to match size of target (15)" {  } { { "clkdiv1ms.v" "" { Text "e:/clk_scan/clkscan2/clkdiv1ms.v" 14 0 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "button:inst4\|enable~reg0 button:inst4\|signal " "Info: Duplicate register \"button:inst4\|enable~reg0\" merged to single register \"button:inst4\|signal\", power-up level changed" {  } { { "button.v" "" { Text "e:/clk_scan/clkscan2/button.v" 4 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "button:inst2\|enable~reg0 button:inst2\|signal " "Info: Duplicate register \"button:inst2\|enable~reg0\" merged to single register \"button:inst2\|signal\", power-up level changed" {  } { { "button.v" "" { Text "e:/clk_scan/clkscan2/button.v" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|clkscan2\|clkscan:inst6\|state 8 0 " "Info: State machine \"\|clkscan2\|clkscan:inst6\|state\" contains 8 states and 0 state bits" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|clkscan2\|clkscan:inst6\|state " "Info: Selected Auto state machine encoding method for state machine \"\|clkscan2\|clkscan:inst6\|state\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|clkscan2\|clkscan:inst6\|state " "Info: Encoding result for state machine \"\|clkscan2\|clkscan:inst6\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "8 " "Info: Completed encoding using 8 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "clkscan:inst6\|state.111 " "Info: Encoded state bit \"clkscan:inst6\|state.111\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "clkscan:inst6\|state.001 " "Info: Encoded state bit \"clkscan:inst6\|state.001\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "clkscan:inst6\|state.010 " "Info: Encoded state bit \"clkscan:inst6\|state.010\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "clkscan:inst6\|state.011 " "Info: Encoded state bit \"clkscan:inst6\|state.011\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "clkscan:inst6\|state.100 " "Info: Encoded state bit \"clkscan:inst6\|state.100\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "clkscan:inst6\|state.101 " "Info: Encoded state bit \"clkscan:inst6\|state.101\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "clkscan:inst6\|state.110 " "Info: Encoded state bit \"clkscan:inst6\|state.110\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "clkscan:inst6\|state.000 " "Info: Encoded state bit \"clkscan:inst6\|state.000\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|clkscan2\|clkscan:inst6\|state.000 00000000 " "Info: State \"\|clkscan2\|clkscan:inst6\|state.000\" uses code string \"00000000\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|clkscan2\|clkscan:inst6\|state.110 00000011 " "Info: State \"\|clkscan2\|clkscan:inst6\|state.110\" uses code string \"00000011\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|clkscan2\|clkscan:inst6\|state.101 00000101 " "Info: State \"\|clkscan2\|clkscan:inst6\|state.101\" uses code string \"00000101\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|clkscan2\|clkscan:inst6\|state.100 00001001 " "Info: State \"\|clkscan2\|clkscan:inst6\|state.100\" uses code string \"00001001\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|clkscan2\|clkscan:inst6\|state.011 00010001 " "Info: State \"\|clkscan2\|clkscan:inst6\|state.011\" uses code string \"00010001\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|clkscan2\|clkscan:inst6\|state.010 00100001 " "Info: State \"\|clkscan2\|clkscan:inst6\|state.010\" uses code string \"00100001\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|clkscan2\|clkscan:inst6\|state.001 01000001 " "Info: State \"\|clkscan2\|clkscan:inst6\|state.001\" uses code string \"01000001\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|clkscan2\|clkscan:inst6\|state.111 10000001 " "Info: State \"\|clkscan2\|clkscan:inst6\|state.111\" uses code string \"10000001\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0}  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "clkscan:inst6\|state.111 clkscan:inst6\|scan_en\[8\] " "Info: Duplicate register \"clkscan:inst6\|state.111\" merged to single register \"clkscan:inst6\|scan_en\[8\]\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "clkscan:inst6\|state.110 clkscan:inst6\|scan_en\[7\] " "Info: Duplicate register \"clkscan:inst6\|state.110\" merged to single register \"clkscan:inst6\|scan_en\[7\]\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "clkscan:inst6\|state.101 clkscan:inst6\|scan_en\[6\] " "Info: Duplicate register \"clkscan:inst6\|state.101\" merged to single register \"clkscan:inst6\|scan_en\[6\]\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "clkscan:inst6\|state.100 clkscan:inst6\|scan_en\[5\] " "Info: Duplicate register \"clkscan:inst6\|state.100\" merged to single register \"clkscan:inst6\|scan_en\[5\]\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "clkscan:inst6\|state.011 clkscan:inst6\|scan_en\[4\] " "Info: Duplicate register \"clkscan:inst6\|state.011\" merged to single register \"clkscan:inst6\|scan_en\[4\]\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "clkscan:inst6\|state.010 clkscan:inst6\|scan_en\[3\] " "Info: Duplicate register \"clkscan:inst6\|state.010\" merged to single register \"clkscan:inst6\|scan_en\[3\]\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "clkscan:inst6\|state.001 clkscan:inst6\|scan_en\[2\] " "Info: Duplicate register \"clkscan:inst6\|state.001\" merged to single register \"clkscan:inst6\|scan_en\[2\]\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "clkscan:inst6\|state.000 clkscan:inst6\|scan_en\[1\] " "Info: Duplicate register \"clkscan:inst6\|state.000\" merged to single register \"clkscan:inst6\|scan_en\[1\]\", power-up level changed" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 17 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "out\[7\] GND " "Warning: Pin \"out\[7\]\" stuck at GND" {  } { { "clkscan2.bdf" "" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { { 296 432 608 312 "out\[7..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 13 -1 0 } } { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 18 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "183 " "Info: Implemented 183 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "164 " "Info: Implemented 164 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 26 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 26 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 14 21:22:48 2008 " "Info: Processing ended: Mon Apr 14 21:22:48 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}