clkscan3.fit.qmsg
来自「采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1:当按下启」· QMSG 代码 · 共 42 行 · 第 1/4 页
QMSG
42 行
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { } { } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" { } { } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" { } { } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: The following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out\[7\] GND " "Info: Pin out\[7\] has GND driving its datain port" { } { { "clkscan3.bdf" "" { Schematic "e:/clk_scan/clkscan3/clkscan3.bdf" { { 392 536 712 408 "out\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out\[7\]" } } } } { "e:/clk_scan/clkscan3/db/clkscan3_cmp.qrpt" "" { Report "e:/clk_scan/clkscan3/db/clkscan3_cmp.qrpt" Compiler "clkscan3" "UNKNOWN" "V1" "e:/clk_scan/clkscan3/db/clkscan3.quartus_db" { Floorplan "e:/clk_scan/clkscan3/" "" "" { out[7] } "NODE_NAME" } "" } } { "e:/clk_scan/clkscan3/clkscan3.fld" "" { Floorplan "e:/clk_scan/clkscan3/clkscan3.fld" "" "" { out[7] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "scan_en\[6\] GND " "Info: Pin scan_en\[6\] has GND driving its datain port" { } { { "clkscan3.bdf" "" { Schematic "e:/clk_scan/clkscan3/clkscan3.bdf" { { 40 728 904 56 "scan_en\[8..1\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "scan_en\[6\]" } } } } { "e:/clk_scan/clkscan3/db/clkscan3_cmp.qrpt" "" { Report "e:/clk_scan/clkscan3/db/clkscan3_cmp.qrpt" Compiler "clkscan3" "UNKNOWN" "V1" "e:/clk_scan/clkscan3/db/clkscan3.quartus_db" { Floorplan "e:/clk_scan/clkscan3/" "" "" { scan_en[6] } "NODE_NAME" } "" } } { "e:/clk_scan/clkscan3/clkscan3.fld" "" { Floorplan "e:/clk_scan/clkscan3/clkscan3.fld" "" "" { scan_en[6] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "scan_en\[3\] GND " "Info: Pin scan_en\[3\] has GND driving its datain port" { } { { "clkscan3.bdf" "" { Schematic "e:/clk_scan/clkscan3/clkscan3.bdf" { { 40 728 904 56 "scan_en\[8..1\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "scan_en\[3\]" } } } } { "e:/clk_scan/clkscan3/db/clkscan3_cmp.qrpt" "" { Report "e:/clk_scan/clkscan3/db/clkscan3_cmp.qrpt" Compiler "clkscan3" "UNKNOWN" "V1" "e:/clk_scan/clkscan3/db/clkscan3.quartus_db" { Floorplan "e:/clk_scan/clkscan3/" "" "" { scan_en[3] } "NODE_NAME" } "" } } { "e:/clk_scan/clkscan3/clkscan3.fld" "" { Floorplan "e:/clk_scan/clkscan3/clkscan3.fld" "" "" { scan_en[3] } "NODE_NAME" } } } 0} } { } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 14 21:14:02 2008 " "Info: Processing ended: Mon Apr 14 21:14:02 2008" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" { } { } 0} } { } 0}
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