clkscan3.fit.qmsg

来自「采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启」· QMSG 代码 · 共 42 行 · 第 1/4 页

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 28 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 28" {  } { { "clkscan3.bdf" "" { Schematic "e:/clk_scan/clkscan3/clkscan3.bdf" { { 16 16 184 32 "clk" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clkdiv1ms:inst1\|clkout Global clock " "Info: Automatically promoted signal \"clkdiv1ms:inst1\|clkout\" to use Global clock" {  } { { "clkdiv1ms.v" "" { Text "e:/clk_scan/clkscan3/clkdiv1ms.v" 4 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clkdiv:inst\|clkout Global clock " "Info: Automatically promoted signal \"clkdiv:inst\|clkout\" to use Global clock" {  } { { "clkdiv.v" "" { Text "e:/clk_scan/clkscan3/clkdiv.v" 4 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "timer:inst6\|min_clk Global clock " "Info: Automatically promoted signal \"timer:inst6\|min_clk\" to use Global clock" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 6 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "timer:inst6\|h_clk Global clock " "Info: Automatically promoted signal \"timer:inst6\|h_clk\" to use Global clock" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 6 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "button:inst9\|signal Global clock " "Info: Automatically promoted some destinations of signal \"button:inst9\|signal\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "timer:inst6\|h_clk " "Info: Destination \"timer:inst6\|h_clk\" may be non-global or may not use global clock" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "button:inst9\|always0~0 " "Info: Destination \"button:inst9\|always0~0\" may be non-global or may not use global clock" {  } {  } 0}  } { { "button.v" "" { Text "e:/clk_scan/clkscan3/button.v" 4 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}