pd064vt5.vhd

用vhdl编写的lcd控制器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity pd064vt5 is
  Generic(
            H_RES  :INTEGER :=800;
            V_RES  :INTEGER :=6--25
);
  port(   tclk,rst: in std_logic;
          sel_reg: in std_logic;
          v_s,h_s,de: out std_logic
          
);
end;

architecture behave of pd064vt5 is 
constant   HPW: integer :=95;
constant   HP : integer :=801;
constant  VPw : integer :=1;
constant   VP : integer :=5;--25;
constant DHPW : integer :=159;
constant  DHP : integer :=801;
constant DVPW : integer :=0;--79;
constant  DVP : integer :=6;--25;
constant  VBP : integer :=3;--4;
constant  VDP : integer :=5;--15;
constant  HBP : integer :=143;
constant  HDP : integer :=785;
signal h_counter: integer range 0 to H_RES;
signal v_counter: integer range 0 to V_RES;
signal h_sync: std_logic;
signal v_sync: std_logic;
signal h_de: std_logic;
signal v_de: std_logic;
signal de_reg: std_logic;
signal fifo_data_available: std_logic;
signal fifo_read_reg: std_logic;

begin

process(tclk,rst,h_counter)
  begin
    if rst='1' then 
       h_counter<=0;
    elsif(tclk'event and tclk='1') then 
       if h_counter=H_RES then
          h_counter<=0;
       else
          h_counter<=h_counter+1;
       end if;
    else
    h_counter<=h_counter;
    end if;
  end process;

process(tclk,rst,h_sync,h_counter)
  begin
    if rst='1' then 
       h_sync<='0';
    elsif (tclk'event and tclk='1') then 
       if(h_counter>HPW and h_counter<HP) then
         h_sync<='1';
       else
         h_sync<='0';
       end if;
     else
     h_sync<=h_sync;
     end if;
  h_s<=h_sync;
end process;

process(tclk,rst,h_counter,v_counter)
  begin
    if rst='1' then 
      v_counter<=0;
    elsif (tclk'event and tclk='1') then 
      if (h_counter=H_RES) then 
        if v_counter=VP then 
          v_counter<=0;
        else 
          v_counter<=v_counter+1;
        end if;
      else
        v_counter<=v_counter;
      end if;
    else
      v_counter<=v_counter;
    end if;
end process;

process(tclk,rst,v_sync)
  begin
    if rst='1' then 
      v_sync<='0';
    elsif (tclk'event and tclk='1') then
      if (v_counter>VPW and v_counter<VP) then
        v_sync<='1';
      else
        v_sync<='0';
      end if;
    else
      v_sync<=v_sync;
    end if;
  v_s<=v_sync;
end process;

process(tclk,rst,h_de,v_de,de_reg)
  begin
    if rst='1' then 
      de_reg<='0';
      h_de<='0';
      v_de<='0';
    elsif(tclk'event and tclk='1') then 
      if(h_counter>DHPW and h_counter<DHP) then 
        h_de<='1';
      else
        h_de<='0';
      end if;
      if(v_counter>DVPW or v_counter<DVP) then 
        v_de<='1';
      else
        v_de<='0';
      end if;
    else
    de_reg<=de_reg;
      h_de<=h_de;
      v_de<=v_de;
    end if;
  de_reg<=h_de and v_de;
  de<=de_reg;
end process;
end;