lcd_controler.vhd

用vhdl编写的lcd控制器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity lcd_controler is 
  port(       clk,rst: in std_logic;
                  add: in std_logic_vector(14 downto 0);
                 data: inout std_logic_vector(7 downto 0);
         we,rd,chip_s: in std_logic;
                add_m: out std_logic_vector(14 downto 0);
               data_m: inout std_logic_vector(7 downto 0);
               we_n_m: out std_logic;
               oe_n_m: out std_logic;
               ce_n_m: out std_logic;
tclk,h_sync,v_sync,de: out std_logic;
                    R: out std_logic_vector(1 downto 0);
                    G: out std_logic_vector(1 downto 0);
                    B: out std_logic_vector(1 downto 0)        
);
end lcd_controler;

architecture behave of lcd_controler is 
signal                add_m_reg:      std_logic_vector(14 downto 0);
signal               data_m_reg:      std_logic_vector(7 downto 0);
signal                 we_m_reg:      std_logic;
signal                 rd_m_reg:      std_logic;
Signal                        D:      std_logic_vector(7 downto 0);
signal                    t_clk:      std_logic;
signal                      w_d:      std_logic_vector(1 downto 0);
signal                    a_reg:      std_logic;
signal                    b_reg:      std_logic;
signal                    clken:      std_logic;
signal                    v_reg:      std_logic;  
signal              add_counter:      std_logic_vector(14 downto 0);
signal                  v_total:      std_logic_vector(19 downto 0);
signal                  sram_rd:      std_logic; 
signal                 sel_temp:      std_logic; 
signal                       qn:      std_logic_vector(1 downto 0);
signal                   de_reg:      std_logic;
signal                      w_r:      std_logic_vector(1 downto 0);
component pd064vt5 is 
  port(            tclk,rst: in std_logic;
                sel_reg: in std_logic;
          v_s,h_s,de: out std_logic
);
end component;

begin
  process(clk,rst,t_clk)
    begin
      if rst='1' then 
         t_clk<='0';
      elsif(clk'event and clk='1') then 
            t_clk<=not t_clk;
         else
            t_clk<=t_clk;
      end if;
            tclk<=t_clk;
  end process;

  process(t_clk,rst,add,we,add_counter,sram_rd,rd_m_reg,we_m_reg)
    begin
      if rst='1' then
        we_m_reg<='1';
        rd_m_reg<='1';
        add_m_reg<=(others=>'0');
      elsif (t_clk'event and t_clk='1') then
        if sel_temp<='0' then
          add_m_reg<=add_counter;
          rd_m_reg<=sram_rd;
        else
          add_m_reg<=add;
          we_m_reg<=we;
          rd_m_reg<=rd;
        end if;
      else
        we_m_reg<=we_m_reg;
        rd_m_reg<=rd_m_reg;
      end if;
  end process;

process(t_clk,rst,data,data_m_reg,data_m,w_r)
  begin
    if rst='1' then 
      data_m_reg<=(others=>'0');
    elsif (t_clk'event and t_clk='1') then
        case w_r is 
          when "01" => data_m_reg<=data;
                       data_m<=data_m_reg;
          when "10" => data_m_reg<=data_m;
                       D<=data_m_reg;
          when others => NULL; 
        end case;
      --if we_m_reg='0' then 
        --data_m_reg<=data;
        --data_m<=data_m_reg;
      --end if;
      --if rd_m_reg='0' then
       --data_m_reg<=data_m;
        --D<=data_m_reg;
      --end if;
    end if;
end process;

process(t_clk,rst,v_total)
  begin
    if rst='1' then
      v_total<=(others=>'0');
    elsif (t_clk'event and t_clk='1') then 
      if sel_temp='0' and (de_reg='1') then 
        --if v_total=307200 then
        if v_total=4480 then 
          v_total<=(others=>'0');
        else
          v_total<=v_total+1;
        end if;
      else
        v_total<=v_total;
      end if;
    end if;
end process;

process(t_clk,rst,add_counter)
  begin
    if rst='1' then 
      add_counter<=(others=>'0');
      sram_rd<='1';
    elsif(t_clk'event and t_clk='1') then 
      --if (v_total>137599 and v_total<169600) then
      if (v_total>639 and v_total<4480) then 
        if add_counter=32000 then 
          add_counter<=(others=>'0');
        else
          add_counter<=add_counter+1;
          sram_rd<='0';
        end if;
      end if;
    end if;
end process;

process(t_clk,rst,clken,a_reg,b_reg,v_reg)
  begin
    if rst='1' then 
      clken<='0';
    elsif (t_clk'event and t_clk='1') then 
      b_reg<=a_reg;
      a_reg<=not v_reg;
    end if;
    clken<=a_reg and not b_reg; 
end process;

process(t_clk,rst,clken,qn)  
  begin
    if rst='1' then 
      qn<="00";
      sel_temp<='0';
    elsif (t_clk'event and t_clk='1') then 
      if clken='1' then 
        if qn=3 then 
          qn<="00";
        else 
          qn<=qn+1;
        end if;
      end if;
    end if;
  sel_temp<=qn(1);
end process;

  process(t_clk,rst,D,sel_temp)
    begin
      if rst='1' then 
        R<=(others=>'0');
        G<=(others=>'0');
        B<=(others=>'0');
      elsif (t_clk'event and t_clk='1') then 
        if (sel_temp='0' and de_reg='1') then 
          R(1)<=D(6);
          G(1)<=D(5);
          B(1)<=D(4);
          R(0)<=D(2);
          G(0)<=D(1);
          B(0)<=D(0);
        else
          R<=(others=>'0');
          G<=(others=>'0');
          B<=(others=>'0');
        end if;
      end if;
    end process;
 
process(add_m_reg,we_m_reg,rd_m_reg,v_reg,sel_temp,sram_rd,de_reg,chip_s)
  begin
    add_m<=add_m_reg;
    we_n_m<=we_m_reg;
    oe_n_m<=rd_m_reg;
    ce_n_m<=chip_s;
    v_sync<=v_reg;
        de<=de_reg;
       w_r<=we_m_reg&rd_m_reg;
end process;
 
U1:pd064vt5
port map (tclk=>t_clk,
          rst=>rst,
          sel_reg=>sel_temp,
          v_s=>v_reg,
          h_s=>h_sync,
          de=>de_reg
);
end;