freedev_cycloneii_50.hier_info

FPGA读写SDRAM的实例

clk => tx_holding_reg[1].CLK
clk => tx_holding_reg[0].CLK
clk => tx_holding_primed.CLK
clk => transmitting.CLK
clk => SCLK_reg.CLK
clk => MISO_reg.CLK
clk => rd_strobe.CLK
data_from_cpu[0] => always13~10.IN1
data_from_cpu[0] => endofpacketvalue_reg[0].DATAIN
data_from_cpu[0] => tx_holding_reg[0].DATAIN
data_from_cpu[0] => asmi_slave_select_holding_reg[0].DATAIN
data_from_cpu[1] => always13~11.IN1
data_from_cpu[1] => asmi_slave_select_holding_reg[1].DATAIN
data_from_cpu[1] => endofpacketvalue_reg[1].DATAIN
data_from_cpu[1] => tx_holding_reg[1].DATAIN
data_from_cpu[2] => always13~12.IN1
data_from_cpu[2] => asmi_slave_select_holding_reg[2].DATAIN
data_from_cpu[2] => endofpacketvalue_reg[2].DATAIN
data_from_cpu[2] => tx_holding_reg[2].DATAIN
data_from_cpu[3] => always13~13.IN1
data_from_cpu[3] => iROE_reg.DATAIN
data_from_cpu[3] => asmi_slave_select_holding_reg[3].DATAIN
data_from_cpu[3] => endofpacketvalue_reg[3].DATAIN
data_from_cpu[3] => tx_holding_reg[3].DATAIN
data_from_cpu[4] => always13~14.IN1
data_from_cpu[4] => iTOE_reg.DATAIN
data_from_cpu[4] => asmi_slave_select_holding_reg[4].DATAIN
data_from_cpu[4] => endofpacketvalue_reg[4].DATAIN
data_from_cpu[4] => tx_holding_reg[4].DATAIN
data_from_cpu[5] => always13~15.IN1
data_from_cpu[5] => asmi_slave_select_holding_reg[5].DATAIN
data_from_cpu[5] => endofpacketvalue_reg[5].DATAIN
data_from_cpu[5] => tx_holding_reg[5].DATAIN
data_from_cpu[6] => always13~16.IN1
data_from_cpu[6] => iTRDY_reg.DATAIN
data_from_cpu[6] => asmi_slave_select_holding_reg[6].DATAIN
data_from_cpu[6] => endofpacketvalue_reg[6].DATAIN
data_from_cpu[6] => tx_holding_reg[6].DATAIN
data_from_cpu[7] => always13~17.IN1
data_from_cpu[7] => iRRDY_reg.DATAIN
data_from_cpu[7] => asmi_slave_select_holding_reg[7].DATAIN
data_from_cpu[7] => endofpacketvalue_reg[7].DATAIN
data_from_cpu[7] => tx_holding_reg[7].DATAIN
data_from_cpu[8] => iE_reg.DATAIN
data_from_cpu[8] => asmi_slave_select_holding_reg[8].DATAIN
data_from_cpu[8] => endofpacketvalue_reg[8].DATAIN
data_from_cpu[9] => iEOP_reg.DATAIN
data_from_cpu[9] => asmi_slave_select_holding_reg[9].DATAIN
data_from_cpu[9] => endofpacketvalue_reg[9].DATAIN
data_from_cpu[10] => always6~0.IN1
data_from_cpu[10] => SSO_reg.DATAIN
data_from_cpu[10] => asmi_slave_select_holding_reg[10].DATAIN
data_from_cpu[10] => endofpacketvalue_reg[10].DATAIN
data_from_cpu[11] => asmi_slave_select_holding_reg[11].DATAIN
data_from_cpu[11] => endofpacketvalue_reg[11].DATAIN
data_from_cpu[12] => asmi_slave_select_holding_reg[12].DATAIN
data_from_cpu[12] => endofpacketvalue_reg[12].DATAIN
data_from_cpu[13] => asmi_slave_select_holding_reg[13].DATAIN
data_from_cpu[13] => endofpacketvalue_reg[13].DATAIN
data_from_cpu[14] => asmi_slave_select_holding_reg[14].DATAIN
data_from_cpu[14] => endofpacketvalue_reg[14].DATAIN
data_from_cpu[15] => asmi_slave_select_holding_reg[15].DATAIN
data_from_cpu[15] => endofpacketvalue_reg[15].DATAIN
mem_addr[0] => reduce_nor~0.IN2
mem_addr[0] => reduce_nor~2.IN2
mem_addr[0] => reduce_nor~4.IN2
mem_addr[0] => reduce_nor~5.IN2
mem_addr[0] => reduce_nor~3.IN2
mem_addr[0] => reduce_nor~1.IN2
mem_addr[1] => reduce_nor~0.IN1
mem_addr[1] => reduce_nor~1.IN1
mem_addr[1] => reduce_nor~5.IN1
mem_addr[1] => reduce_nor~4.IN1
mem_addr[1] => reduce_nor~3.IN1
mem_addr[1] => reduce_nor~2.IN1
mem_addr[2] => reduce_nor~0.IN0
mem_addr[2] => reduce_nor~1.IN0
mem_addr[2] => reduce_nor~2.IN0
mem_addr[2] => reduce_nor~3.IN0
mem_addr[2] => reduce_nor~5.IN0
mem_addr[2] => reduce_nor~4.IN0
read_n => p1_rd_strobe.IN1
reset_n => shift_reg[6].ACLR
reset_n => shift_reg[5].ACLR
reset_n => shift_reg[4].ACLR
reset_n => shift_reg[3].ACLR
reset_n => shift_reg[2].ACLR
reset_n => shift_reg[1].ACLR
reset_n => shift_reg[0].ACLR
reset_n => rx_holding_reg[7].ACLR
reset_n => rx_holding_reg[6].ACLR
reset_n => rx_holding_reg[5].ACLR
reset_n => rx_holding_reg[4].ACLR
reset_n => rx_holding_reg[3].ACLR
reset_n => rx_holding_reg[2].ACLR
reset_n => rx_holding_reg[1].ACLR
reset_n => rx_holding_reg[0].ACLR
reset_n => EOP.ACLR
reset_n => RRDY.ACLR
reset_n => ROE.ACLR
reset_n => TOE.ACLR
reset_n => tx_holding_reg[7].ACLR
reset_n => tx_holding_reg[6].ACLR
reset_n => tx_holding_reg[5].ACLR
reset_n => tx_holding_reg[4].ACLR
reset_n => tx_holding_reg[3].ACLR
reset_n => tx_holding_reg[2].ACLR
reset_n => tx_holding_reg[1].ACLR
reset_n => tx_holding_reg[0].ACLR
reset_n => tx_holding_primed.ACLR
reset_n => transmitting.ACLR
reset_n => SCLK_reg.ACLR
reset_n => MISO_reg.ACLR
reset_n => data_to_cpu[14]~reg0.ACLR
reset_n => shift_reg[7].ACLR
reset_n => data_to_cpu[13]~reg0.ACLR
reset_n => data_to_cpu[12]~reg0.ACLR
reset_n => data_to_cpu[11]~reg0.ACLR
reset_n => data_to_cpu[10]~reg0.ACLR
reset_n => data_to_cpu[9]~reg0.ACLR
reset_n => data_to_cpu[8]~reg0.ACLR
reset_n => data_to_cpu[7]~reg0.ACLR
reset_n => data_to_cpu[6]~reg0.ACLR
reset_n => data_to_cpu[5]~reg0.ACLR
reset_n => data_to_cpu[4]~reg0.ACLR
reset_n => data_to_cpu[3]~reg0.ACLR
reset_n => data_to_cpu[2]~reg0.ACLR
reset_n => data_to_cpu[1]~reg0.ACLR
reset_n => data_to_cpu[0]~reg0.ACLR
reset_n => data_to_cpu[15]~reg0.ACLR
reset_n => irq_reg.ACLR
reset_n => data_rd_strobe.ACLR
reset_n => wr_strobe.ACLR
reset_n => data_wr_strobe.ACLR
reset_n => iE_reg.ACLR
reset_n => iRRDY_reg.ACLR
reset_n => iTRDY_reg.ACLR
reset_n => iTOE_reg.ACLR
reset_n => iROE_reg.ACLR
reset_n => SSO_reg.ACLR
reset_n => iEOP_reg.ACLR
reset_n => asmi_slave_select_reg[14].ACLR
reset_n => asmi_slave_select_reg[13].ACLR
reset_n => asmi_slave_select_reg[12].ACLR
reset_n => asmi_slave_select_reg[11].ACLR
reset_n => asmi_slave_select_reg[10].ACLR
reset_n => asmi_slave_select_reg[9].ACLR
reset_n => asmi_slave_select_reg[8].ACLR
reset_n => asmi_slave_select_reg[7].ACLR
reset_n => asmi_slave_select_reg[6].ACLR
reset_n => asmi_slave_select_reg[5].ACLR
reset_n => asmi_slave_select_reg[4].ACLR
reset_n => asmi_slave_select_reg[3].ACLR
reset_n => asmi_slave_select_reg[2].ACLR
reset_n => asmi_slave_select_reg[1].ACLR
reset_n => asmi_slave_select_reg[0].PRESET
reset_n => asmi_slave_select_reg[15].ACLR
reset_n => asmi_slave_select_holding_reg[14].ACLR
reset_n => asmi_slave_select_holding_reg[13].ACLR
reset_n => asmi_slave_select_holding_reg[12].ACLR
reset_n => asmi_slave_select_holding_reg[11].ACLR
reset_n => asmi_slave_select_holding_reg[10].ACLR
reset_n => asmi_slave_select_holding_reg[9].ACLR
reset_n => asmi_slave_select_holding_reg[8].ACLR
reset_n => asmi_slave_select_holding_reg[7].ACLR
reset_n => asmi_slave_select_holding_reg[6].ACLR
reset_n => asmi_slave_select_holding_reg[5].ACLR
reset_n => asmi_slave_select_holding_reg[4].ACLR
reset_n => asmi_slave_select_holding_reg[3].ACLR
reset_n => asmi_slave_select_holding_reg[2].ACLR
reset_n => asmi_slave_select_holding_reg[1].ACLR
reset_n => asmi_slave_select_holding_reg[0].PRESET
reset_n => asmi_slave_select_holding_reg[15].ACLR
reset_n => slowcount[0].ACLR
reset_n => slowcount[1].ACLR
reset_n => endofpacketvalue_reg[14].ACLR
reset_n => endofpacketvalue_reg[13].ACLR
reset_n => endofpacketvalue_reg[12].ACLR
reset_n => endofpacketvalue_reg[11].ACLR
reset_n => endofpacketvalue_reg[10].ACLR
reset_n => endofpacketvalue_reg[9].ACLR
reset_n => endofpacketvalue_reg[8].ACLR
reset_n => endofpacketvalue_reg[7].ACLR
reset_n => endofpacketvalue_reg[6].ACLR
reset_n => endofpacketvalue_reg[5].ACLR
reset_n => endofpacketvalue_reg[4].ACLR
reset_n => endofpacketvalue_reg[3].ACLR
reset_n => endofpacketvalue_reg[2].ACLR
reset_n => endofpacketvalue_reg[1].ACLR
reset_n => endofpacketvalue_reg[0].ACLR
reset_n => endofpacketvalue_reg[15].ACLR
reset_n => delayCounter[10].ACLR
reset_n => delayCounter[9].ACLR
reset_n => delayCounter[8].PRESET
reset_n => delayCounter[7].PRESET
reset_n => delayCounter[6].PRESET
reset_n => delayCounter[5].ACLR
reset_n => delayCounter[4].ACLR
reset_n => delayCounter[3].ACLR
reset_n => delayCounter[2].ACLR
reset_n => delayCounter[1].PRESET
reset_n => delayCounter[0].PRESET
reset_n => delayCounter[11].PRESET
reset_n => state[3].ACLR
reset_n => state[2].ACLR
reset_n => state[1].ACLR
reset_n => state[0].ACLR
reset_n => state[4].ACLR