freedev_cycloneii_50.hif

FPGA读写SDRAM的实例

byteena_a1
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
}
# memory_file {
payload_buffer.hex
1155288833
}
# hierarchies {
freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated
}
# end
# entity
decode_1oa
# case_insensitive
# source_file
db|decode_1oa.tdf
1155289445
6
# storage
db|freedev_cycloneII_50.(38).cnf
db|freedev_cycloneII_50.(38).cnf
# used_port {
data0
enable
eq0
eq1
}
# hierarchies {
freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|decode_1oa:decode3
}
# end
# entity
mux_0kb
# case_insensitive
# source_file
db|mux_0kb.tdf
1155289445
6
# storage
db|freedev_cycloneII_50.(39).cnf
db|freedev_cycloneII_50.(39).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data20
data21
data22
data23
data24
data25
data26
data27
data28
data29
data30
data31
sel0
result0
result1
result2
result3
result4
result5
result6
result7
result8
result9
result10
result11
result12
result13
result14
result15
}
# hierarchies {
freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|mux_0kb:mux2
}
# end
# entity
sysid_control_slave_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
freedev_cycloneII_50.v
1155288846
7
# storage
db|freedev_cycloneII_50.(40).cnf
db|freedev_cycloneII_50.(40).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|sysid_control_slave_arbitrator:the_sysid_control_slave
}
# end
# entity
sysid
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sysid.v
1155288835
7
# storage
db|freedev_cycloneII_50.(41).cnf
db|freedev_cycloneII_50.(41).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|sysid:the_sysid
}
# end
# entity
tri_state_bridge_0_avalon_slave_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
freedev_cycloneII_50.v
1155288846
7
# storage
db|freedev_cycloneII_50.(42).cnf
db|freedev_cycloneII_50.(42).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave
}
# end
# entity
freedev_cycloneII_50_reset_clk_domain_synch_module
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
freedev_cycloneII_50.v
1155288846
7
# storage
db|freedev_cycloneII_50.(43).cnf
db|freedev_cycloneII_50.(43).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|freedev_cycloneII_50_reset_clk_domain_synch_module:freedev_cycloneII_50_reset_clk_domain_synch
}
# end
# entity
delay_reset_block
# case_insensitive
# source_file
delay_reset_block.bdf
1155108513
23
# storage
db|freedev_cycloneII_50.(44).cnf
db|freedev_cycloneII_50.(44).cnf
# hierarchies {
delay_reset_block:inst3
}
# end
# entity
reset_counter
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
reset_counter.v
1155108513
7
# storage
db|freedev_cycloneII_50.(45).cnf
db|freedev_cycloneII_50.(45).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
delay_reset_block:inst3|reset_counter:inst
}
# end
# entity
lpm_counter
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_counter.tdf
1114012448
6
# storage
db|freedev_cycloneII_50.(46).cnf
db|freedev_cycloneII_50.(46).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
10
PARAMETER_DEC
USR
LPM_DIRECTION
UP
PARAMETER_UNKNOWN
USR
LPM_MODULUS
0
PARAMETER_UNKNOWN
DEF
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_vm8
PARAMETER_UNKNOWN
USR
}
# used_port {
aclr
clock
cnt_en
cout
q
q
q
q
q
q
q
q
q
q
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
c:|altera|quartus50|libraries|megafunctions|lpm_add_sub.inc
1107574408
c:|altera|quartus50|libraries|megafunctions|cmpconst.inc
1107573980
c:|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107574500
c:|altera|quartus50|libraries|megafunctions|lpm_counter.inc
1107574548
c:|altera|quartus50|libraries|megafunctions|dffeea.inc
1107574164
c:|altera|quartus50|libraries|megafunctions|alt_synch_counter.inc
1107572664
c:|altera|quartus50|libraries|megafunctions|alt_synch_counter_f.inc
1107572680
c:|altera|quartus50|libraries|megafunctions|alt_counter_f10ke.inc
1107572320
c:|altera|quartus50|libraries|megafunctions|alt_counter_stratix.inc
1107572334
}
# hierarchies {
delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component
}
# end
# entity
cntr_vm8
# case_insensitive
# source_file
db|cntr_vm8.tdf
1155289447
6
# storage
db|freedev_cycloneII_50.(47).cnf
db|freedev_cycloneII_50.(47).cnf
# used_port {
clock
cnt_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
cout
}
# hierarchies {
delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_vm8:auto_generated
}
# end
# entity
sld_hub
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
4
# storage
db|freedev_cycloneII_50.(48).cnf
db|freedev_cycloneII_50.(48).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
2
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone II
PARAMETER_UNKNOWN
USR
n_nodes
1
PARAMETER_UNKNOWN
USR
n_sel_bits
1
PARAMETER_UNKNOWN
USR
n_node_ir_bits
4
PARAMETER_UNKNOWN
USR
node_info
00001100000000000110111000000000
PARAMETER_BIN
USR
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
}
# end
# entity
sld_jtag_state_machine
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
4
# storage
db|freedev_cycloneII_50.(49).cnf
db|freedev_cycloneII_50.(49).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
1
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_shiftreg.tdf
1114012454
6
# storage
db|freedev_cycloneII_50.(50).cnf
db|freedev_cycloneII_50.(50).cnf
# user_parameter {
LPM_WIDTH
10
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
enable
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
shiftin
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
c:|altera|quartus50|libraries|megafunctions|dffeea.inc
1107574164
}
# end
# entity
lpm_decode
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_decode.tdf
1114012450
6
# storage
db|freedev_cycloneII_50.(51).cnf
db|freedev_cycloneII_50.(51).cnf
# user_parameter {
LPM_WIDTH
3
PARAMETER_DEC
USR
LPM_DECODES
8
PARAMETER_DEC
USR
LPM_PIPELINE
1
PARAMETER_DEC
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
decode_rpe
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq7
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
c:|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107574500
c:|altera|quartus50|libraries|megafunctions|declut.inc
1107574136
c:|altera|quartus50|libraries|megafunctions|altshift.inc
1107573438
}
# end
# entity
decode_rpe
# case_insensitive
# source_file
db|decode_rpe.tdf
1155289450
6
# storage
db|freedev_cycloneII_50.(52).cnf
db|freedev_cycloneII_50.(52).cnf
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq4
eq5
eq6
eq7
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1114012236
4
# storage
db|freedev_cycloneII_50.(53).cnf
db|freedev_cycloneII_50.(53).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
1
PARAMETER_DEC
USR
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1114012236
4
# storage
db|freedev_cycloneII_50.(54).cnf
db|freedev_cycloneII_50.(54).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
5
PARAMETER_DEC
USR
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1114012236
4
# storage
db|freedev_cycloneII_50.(55).cnf
db|freedev_cycloneII_50.(55).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
4
PARAMETER_DEC
USR
}
# end
# entity
sld_rom_sr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_rom_sr.vhd
1114012236
4
# storage
db|freedev_cycloneII_50.(56).cnf
db|freedev_cycloneII_50.(56).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
64
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# end
# entity
altsyncram_toc1
# case_insensitive
# source_file
db|altsyncram_toc1.tdf
1155289444
6
# storage
db|freedev_cycloneII_50.(30).cnf
db|freedev_cycloneII_50.(30).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
clock0
clock1
clocken1
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
wren_a
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
}
# memory_file {
none
0
}
# hierarchies {
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2
}
# end
# complete