freedev_cycloneii_50.hif

FPGA读写SDRAM的实例

db|freedev_cycloneII_50.(21).cnf
db|freedev_cycloneII_50.(21).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave
}
# end
# entity
jtag_uart_0
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart_0.v
1155288834
7
# storage
db|freedev_cycloneII_50.(22).cnf
db|freedev_cycloneII_50.(22).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0
}
# end
# entity
jtag_uart_0_scfifo_w
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart_0.v
1155288834
7
# storage
db|freedev_cycloneII_50.(23).cnf
db|freedev_cycloneII_50.(23).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w
}
# end
# entity
scfifo
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|scfifo.tdf
1114012440
6
# storage
db|freedev_cycloneII_50.(24).cnf
db|freedev_cycloneII_50.(24).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
8
PARAMETER_DEC
USR
LPM_NUMWORDS
64
PARAMETER_DEC
USR
LPM_WIDTHU
6
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_j4p
PARAMETER_UNKNOWN
USR
}
# used_port {
clock
data
data
data
data
data
data
data
data
empty
full
q
q
q
q
q
q
q
q
rdreq
usedw
usedw
usedw
usedw
usedw
usedw
wrreq
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|a_dpfifo.inc
1107571908
c:|altera|quartus50|libraries|megafunctions|a_i2fifo.inc
1107572036
c:|altera|quartus50|libraries|megafunctions|a_regfifo.inc
1107572164
c:|altera|quartus50|libraries|megafunctions|a_fffifo.inc
1107571974
c:|altera|quartus50|libraries|megafunctions|a_f2fifo.inc
1107571944
}
# hierarchies {
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo
}
# end
# entity
scfifo_j4p
# case_insensitive
# source_file
db|scfifo_j4p.tdf
1155289444
6
# storage
db|freedev_cycloneII_50.(25).cnf
db|freedev_cycloneII_50.(25).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
wrreq
rdreq
clock
q0
q1
q2
q3
q4
q5
q6
q7
empty
full
usedw0
usedw1
usedw2
usedw3
usedw4
usedw5
}
# hierarchies {
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated
}
# end
# entity
a_dpfifo_qap
# case_insensitive
# source_file
db|a_dpfifo_qap.tdf
1155289444
6
# storage
db|freedev_cycloneII_50.(26).cnf
db|freedev_cycloneII_50.(26).cnf
# used_port {
clock
data0
data1
data2
data3
data4
data5
data6
data7
rreq
sclr
wreq
empty
full
q0
q1
q2
q3
q4
q5
q6
q7
usedw0
usedw1
usedw2
usedw3
usedw4
usedw5
}
# hierarchies {
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo
}
# end
# entity
a_fefifo_7cf
# case_insensitive
# source_file
db|a_fefifo_7cf.tdf
1155289444
6
# storage
db|freedev_cycloneII_50.(27).cnf
db|freedev_cycloneII_50.(27).cnf
# used_port {
aclr
clock
rreq
sclr
wreq
empty
full
usedw_out0
usedw_out1
usedw_out2
usedw_out3
usedw_out4
usedw_out5
}
# hierarchies {
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state
}
# end
# entity
cntr_rj7
# case_insensitive
# source_file
db|cntr_rj7.tdf
1155289444
6
# storage
db|freedev_cycloneII_50.(28).cnf
db|freedev_cycloneII_50.(28).cnf
# used_port {
aclr
clock
cnt_en
sclr
updown
q0
q1
q2
q3
q4
q5
}
# hierarchies {
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw
}
# end
# entity
dpram_pcp
# case_insensitive
# source_file
db|dpram_pcp.tdf
1155289444
6
# storage
db|freedev_cycloneII_50.(29).cnf
db|freedev_cycloneII_50.(29).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
inclock
outclock
outclocken
rdaddress0
rdaddress1
rdaddress2
rdaddress3
rdaddress4
rdaddress5
wraddress0
wraddress1
wraddress2
wraddress3
wraddress4
wraddress5
wren
q0
q1
q2
q3
q4
q5
q6
q7
}
# hierarchies {
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram
}
# end
# entity
cntr_dl8
# case_insensitive
# source_file
db|cntr_dl8.tdf
1155289444
6
# storage
db|freedev_cycloneII_50.(31).cnf
db|freedev_cycloneII_50.(31).cnf
# used_port {
aclr
clock
cnt_en
sclr
q0
q1
q2
q3
q4
q5
}
# hierarchies {
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr
}
# end
# entity
jtag_uart_0_scfifo_r
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart_0.v
1155288834
7
# storage
db|freedev_cycloneII_50.(32).cnf
db|freedev_cycloneII_50.(32).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r
}
# end
# entity
alt_jtag_atlantic
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|alt_jtag_atlantic.v
1114012242
7
# storage
db|freedev_cycloneII_50.(33).cnf
db|freedev_cycloneII_50.(33).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
INSTANCE_ID
0
PARAMETER_DEC
USR
SLD_NODE_INFO
00001100000000000110111000000000
PARAMETER_BIN
DEF
LOG2_TXFIFO_DEPTH
6
PARAMETER_DEC
USR
LOG2_RXFIFO_DEPTH
6
PARAMETER_DEC
USR
RESERVED
0
PARAMETER_DEC
DEF
DATA_WIDTH
8
PARAMETER_DEC
DEF
NODE_IR_WIDTH
1
PARAMETER_DEC
DEF
SCAN_LENGTH
11
PARAMETER_DEC
DEF
}
# hierarchies {
freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic
}
# end
# entity
payload_buffer_s1_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
freedev_cycloneII_50.v
1155288846
7
# storage
db|freedev_cycloneII_50.(34).cnf
db|freedev_cycloneII_50.(34).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1
}
# end
# entity
payload_buffer
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
payload_buffer.v
1155288833
7
# storage
db|freedev_cycloneII_50.(35).cnf
db|freedev_cycloneII_50.(35).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|freedev_cycloneII_50.(36).cnf
db|freedev_cycloneII_50.(36).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
SINGLE_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_DEC
USR
WIDTHAD_A
13
PARAMETER_DEC
USR
NUMWORDS_A
8192
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
2
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
payload_buffer.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_p111
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
byteena_a
byteena_a
clock0
clocken0
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
wren_a
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_p111
# case_insensitive
# source_file
db|altsyncram_p111.tdf
1155289445
6
# storage
db|freedev_cycloneII_50.(37).cnf
db|freedev_cycloneII_50.(37).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_a10
address_a11
address_a12
clock0
clocken0
byteena_a0