freedev_cycloneii_50.map.qmsg

FPGA读写SDRAM的实例

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(356) " "Warning: Verilog HDL assignment warning at asmi.v(356): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 356 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(360) " "Warning: Verilog HDL assignment warning at asmi.v(360): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 360 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(364) " "Warning: Verilog HDL assignment warning at asmi.v(364): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 364 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(368) " "Warning: Verilog HDL assignment warning at asmi.v(368): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 368 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(372) " "Warning: Verilog HDL assignment warning at asmi.v(372): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 372 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(376) " "Warning: Verilog HDL assignment warning at asmi.v(376): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 376 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(381) " "Warning: Verilog HDL assignment warning at asmi.v(381): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 381 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(383) " "Warning: Verilog HDL assignment warning at asmi.v(383): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 383 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(384) " "Warning: Verilog HDL assignment warning at asmi.v(384): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 384 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(385) " "Warning: Verilog HDL assignment warning at asmi.v(385): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 385 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(391) " "Warning: Verilog HDL assignment warning at asmi.v(391): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 391 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(392) " "Warning: Verilog HDL assignment warning at asmi.v(392): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 392 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(394) " "Warning: Verilog HDL assignment warning at asmi.v(394): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 394 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(396) " "Warning: Verilog HDL assignment warning at asmi.v(396): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 396 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "asmi.v(403) " "Warning: (10037) Verilog HDL or VHDL warning at asmi.v(403): condition expression evaluates to a constant" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 403 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tornado_asmi_atom freedev_cycloneII_50:inst\|asmi:the_asmi\|tornado_asmi_atom:the_tornado_asmi_atom " "Info: Elaborating entity \"tornado_asmi_atom\" for hierarchy \"freedev_cycloneII_50:inst\|asmi:the_asmi\|tornado_asmi_atom:the_tornado_asmi_atom\"" {  } { { "asmi.v" "the_tornado_asmi_atom" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 529 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_data_master_arbitrator freedev_cycloneII_50:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master " "Info: Elaborating entity \"cpu_0_data_master_arbitrator\" for hierarchy \"freedev_cycloneII_50:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\"" {  } { { "freedev_cycloneII_50.v" "the_cpu_0_data_master" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 3507 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(434) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(434): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 434 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(440) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(440): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 440 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "28 1 freedev_cycloneII_50.v(448) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(448): truncated value with size 28 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 448 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(497) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(497): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 497 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "freedev_cycloneII_50.v(498) " "Warning: (10037) Verilog HDL or VHDL warning at freedev_cycloneII_50.v(498): condition expression evaluates to a constant" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 498 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(499) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(499): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 499 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "freedev_cycloneII_50.v(545) " "Warning: (10037) Verilog HDL or VHDL warning at freedev_cycloneII_50.v(545): condition expression evaluates to a constant" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 545 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(557) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(557): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 557 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "freedev_cycloneII_50.v(558) " "Warning: (10037) Verilog HDL or VHDL warning at freedev_cycloneII_50.v(558): condition expression evaluates to a constant" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 558 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(568) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(568): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 568 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 freedev_cycloneII_50.v(583) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(583): truncated value with size 32 to match size of target (16)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 583 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 freedev_cycloneII_50.v(596) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(596): truncated value with size 32 to match size of target (2)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 596 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 freedev_cycloneII_50.v(614) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(614): truncated value with size 32 to match size of target (2)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 614 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_instruction_master_arbitrator freedev_cycloneII_50:inst\|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master " "Info: Elaborating entity \"cpu_0_instruction_master_arbitrator\" for hierarchy \"freedev_cycloneII_50:inst\|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master\"" {  } { { "freedev_cycloneII_50.v" "the_cpu_0_instruction_master" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 3545 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "active_and_waiting_last_time freedev_cycloneII_50.v(701) " "Info: (10035) Verilog HDL or VHDL information at freedev_cycloneII_50.v(701): object \"active_and_waiting_last_time\" declared but not used" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 701 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cpu_0_instruction_master_address_last_time freedev_cycloneII_50.v(702) " "Info: (10035) Verilog HDL or VHDL information at freedev_cycloneII_50.v(702): object \"cpu_0_instruction_master_address_last_time\" declared but not used" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 702 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cpu_0_instruction_master_read_last_time freedev_cycloneII_50.v(706) " "Info: (10035) Verilog HDL or VHDL information at freedev_cycloneII_50.v(706): object \"cpu_0_instruction_master_read_last_time\" declared but not used" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 706 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(720) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(720): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 720 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(726) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(726): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 726 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "28 1 freedev_cycloneII_50.v(734) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(734): truncated value with size 28 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 734 0 0 } }  } 0}