sramcontroller.rpt

SRAM_controller,资源多多共享,不亦乐乎!

  _EQ035 =  _LC5_A15 &  _LC6_A15
         # !_LC6_A15 &  _LC7_A20 &  _LC8_A13;

-- Node name is ':60' 
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = DFFE( _EQ036, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ036 = !_LC1_A20 &  _LC3_A20 &  _LC8_A13
         #  _LC1_A20 &  _LC8_A20;

-- Node name is ':62' 
-- Equation name is '_LC4_A20', type is buried 
_LC4_A20 = DFFE( _EQ037, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ037 =  _LC4_A20 &  _LC6_A20
         #  _LC2_A20 & !_LC4_A20 &  _LC8_A13;

-- Node name is ':64' 
-- Equation name is '_LC5_A20', type is buried 
_LC5_A20 = DFFE( _EQ038, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ038 =  _LC5_A20 &  _LC5_A22
         #  _LC4_A22 & !_LC5_A20 &  _LC8_A13;

-- Node name is ':66' 
-- Equation name is '_LC3_A22', type is buried 
_LC3_A22 = DFFE( _EQ039, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ039 =  _LC1_A22 & !_LC3_A22 &  _LC8_A13
         #  _LC3_A22 &  _LC8_A22;

-- Node name is ':68' 
-- Equation name is '_LC6_A22', type is buried 
_LC6_A22 = DFFE( _EQ040, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ040 =  _LC2_A22 &  _LC6_A22
         # !_LC6_A22 &  _LC7_A22 &  _LC8_A13;

-- Node name is ':70' 
-- Equation name is '_LC7_A22', type is buried 
_LC7_A22 = DFFE( _EQ041, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ041 =  _LC3_A14 &  _LC7_A22
         # !_LC3_A14 & !_LC7_A22;

-- Node name is ':72' 
-- Equation name is '_LC7_A19', type is buried 
_LC7_A19 = DFFE( _EQ042, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ042 =  _LC6_A14
         # !_LC5_A14 &  _LC7_A19
         # !_LC5_A14 &  _LC7_A14;

-- Node name is '~267~1' 
-- Equation name is '~267~1', location is LC1_A13, type is buried.
-- synthesized logic cell 
_LC1_A13 = LCELL( _EQ043);
  _EQ043 =  counter2
         #  counter3;

-- Node name is '~267~2' 
-- Equation name is '~267~2', location is LC8_A13, type is buried.
-- synthesized logic cell 
_LC8_A13 = LCELL( _EQ044);
  _EQ044 =  _LC1_A13 &  _LC5_A18;

-- Node name is ':267' 
-- Equation name is '_LC6_A14', type is buried 
_LC6_A14 = LCELL( _EQ045);
  _EQ045 = !counter0 & !counter1 & !counter2 & !counter3;

-- Node name is '~276~1' 
-- Equation name is '~276~1', location is LC7_A14, type is buried.
-- synthesized logic cell 
_LC7_A14 = LCELL( _EQ046);
  _EQ046 =  counter0 &  counter1 & !counter2 & !counter3;

-- Node name is ':276' 
-- Equation name is '_LC5_A14', type is buried 
!_LC5_A14 = _LC5_A14~NOT;
_LC5_A14~NOT = LCELL( _EQ047);
  _EQ047 =  counter1
         # !counter0
         #  counter2
         #  counter3;

-- Node name is ':303' 
-- Equation name is '_LC6_A18', type is buried 
_LC6_A18 = LCELL( _EQ048);
  _EQ048 = !counter0 & !counter1 &  counter2 & !counter3;

-- Node name is '~747~1' 
-- Equation name is '~747~1', location is LC5_A18, type is buried.
-- synthesized logic cell 
_LC5_A18 = LCELL( _EQ049);
  _EQ049 = !_LC3_A18 &  _LC6_A18
         # !_LC1_A18 &  _LC6_A18;

-- Node name is '~770~1' 
-- Equation name is '~770~1', location is LC8_A18, type is buried.
-- synthesized logic cell 
_LC8_A18 = LCELL( _EQ050);
  _EQ050 = !_LC1_A18 &  _LC6_A18
         #  _LC3_A14;

-- Node name is '~788~1' 
-- Equation name is '~788~1', location is LC7_A18, type is buried.
-- synthesized logic cell 
_LC7_A18 = LCELL( _EQ051);
  _EQ051 = !_LC2_A18 &  _LC5_A18
         #  _LC3_A14;

-- Node name is '~806~1' 
-- Equation name is '~806~1', location is LC8_A15, type is buried.
-- synthesized logic cell 
_LC8_A15 = LCELL( _EQ052);
  _EQ052 = !_LC4_A15 &  _LC5_A18
         #  _LC3_A14;

-- Node name is '~824~1' 
-- Equation name is '~824~1', location is LC7_A15, type is buried.
-- synthesized logic cell 
_LC7_A15 = LCELL( _EQ053);
  _EQ053 = !_LC2_A15 &  _LC5_A18
         #  _LC3_A14;

-- Node name is '~842~1' 
-- Equation name is '~842~1', location is LC5_A15, type is buried.
-- synthesized logic cell 
_LC5_A15 = LCELL( _EQ054);
  _EQ054 =  _LC5_A18 & !_LC7_A20
         #  _LC3_A14;

-- Node name is '~860~1' 
-- Equation name is '~860~1', location is LC8_A20, type is buried.
-- synthesized logic cell 
_LC8_A20 = LCELL( _EQ055);
  _EQ055 = !_LC3_A20 &  _LC5_A18
         #  _LC3_A14;

-- Node name is '~878~1' 
-- Equation name is '~878~1', location is LC6_A20, type is buried.
-- synthesized logic cell 
_LC6_A20 = LCELL( _EQ056);
  _EQ056 = !_LC2_A20 &  _LC5_A18
         #  _LC3_A14;

-- Node name is '~896~1' 
-- Equation name is '~896~1', location is LC5_A22, type is buried.
-- synthesized logic cell 
_LC5_A22 = LCELL( _EQ057);
  _EQ057 = !_LC4_A22 &  _LC5_A18
         #  _LC3_A14;

-- Node name is '~914~1' 
-- Equation name is '~914~1', location is LC8_A22, type is buried.
-- synthesized logic cell 
_LC8_A22 = LCELL( _EQ058);
  _EQ058 = !_LC1_A22 &  _LC5_A18
         #  _LC3_A14;

-- Node name is '~932~1' 
-- Equation name is '~932~1', location is LC2_A22, type is buried.
-- synthesized logic cell 
_LC2_A22 = LCELL( _EQ059);
  _EQ059 =  _LC5_A18 & !_LC7_A22
         #  _LC3_A14;

-- Node name is '~950~1' 
-- Equation name is '~950~1', location is LC3_A14, type is buried.
-- synthesized logic cell 
!_LC3_A14 = _LC3_A14~NOT;
_LC3_A14~NOT = LCELL( _EQ060);
  _EQ060 = !counter0 & !counter1 &  counter2 & !counter3;

-- Node name is '~1112~1' 
-- Equation name is '~1112~1', location is LC8_A14, type is buried.
-- synthesized logic cell 
!_LC8_A14 = _LC8_A14~NOT;
_LC8_A14~NOT = LCELL( _EQ061);
  _EQ061 = !counter0 &  counter1 & !counter2 & !counter3;



Project Information e:\my documents\my_vhdl\sram_controller\sramcontroller.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 12,236K