📄 srm_read_and_write.rpt
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-- Node name is '|SRAMCONTROLLER:1|:60'
-- Equation name is '_LC2_B15', type is buried
_LC2_B15 = DFFE( _EQ036, GLOBAL( CLOCK), VCC, VCC, VCC);
_EQ036 = !_LC2_B15 & _LC4_B15 & _LC6_B8
# _LC2_B15 & _LC7_B15;
-- Node name is '|SRAMCONTROLLER:1|:62'
-- Equation name is '_LC1_B15', type is buried
_LC1_B15 = DFFE( _EQ037, GLOBAL( CLOCK), VCC, VCC, VCC);
_EQ037 = _LC1_B15 & _LC5_B15
# !_LC1_B15 & _LC3_B15 & _LC6_B8;
-- Node name is '|SRAMCONTROLLER:1|:64'
-- Equation name is '_LC6_B15', type is buried
_LC6_B15 = DFFE( _EQ038, GLOBAL( CLOCK), VCC, VCC, VCC);
_EQ038 = _LC2_B17 & _LC6_B15
# _LC6_B8 & !_LC6_B15 & _LC8_B17;
-- Node name is '|SRAMCONTROLLER:1|:66'
-- Equation name is '_LC7_B17', type is buried
_LC7_B17 = DFFE( _EQ039, GLOBAL( CLOCK), VCC, VCC, VCC);
_EQ039 = _LC1_B17 & _LC6_B8 & !_LC7_B17
# _LC6_B17 & _LC7_B17;
-- Node name is '|SRAMCONTROLLER:1|:68'
-- Equation name is '_LC3_B17', type is buried
_LC3_B17 = DFFE( _EQ040, GLOBAL( CLOCK), VCC, VCC, VCC);
_EQ040 = _LC3_B17 & _LC4_B17
# !_LC3_B17 & _LC5_B17 & _LC6_B8;
-- Node name is '|SRAMCONTROLLER:1|:70'
-- Equation name is '_LC5_B17', type is buried
_LC5_B17 = DFFE( _EQ041, GLOBAL( CLOCK), VCC, VCC, VCC);
_EQ041 = _LC4_B2 & _LC5_B17
# !_LC4_B2 & !_LC5_B17;
-- Node name is '|SRAMCONTROLLER:1|:72'
-- Equation name is '_LC2_B5', type is buried
_LC2_B5 = DFFE( _EQ042, GLOBAL( CLOCK), VCC, VCC, VCC);
_EQ042 = _LC2_B5 & !_LC5_B2
# !_LC5_B2 & _LC7_B2
# _LC6_B2;
-- Node name is '|SRAMCONTROLLER:1|~267~1'
-- Equation name is '_LC2_B8', type is buried
-- synthesized logic cell
_LC2_B8 = LCELL( _EQ043);
_EQ043 = _LC1_B2
# _LC2_B2;
-- Node name is '|SRAMCONTROLLER:1|~267~2'
-- Equation name is '_LC6_B8', type is buried
-- synthesized logic cell
_LC6_B8 = LCELL( _EQ044);
_EQ044 = _LC2_B8 & _LC6_B12;
-- Node name is '|SRAMCONTROLLER:1|:267'
-- Equation name is '_LC6_B2', type is buried
_LC6_B2 = LCELL( _EQ045);
_EQ045 = !_LC1_B2 & !_LC1_B4 & !_LC2_B2 & !_LC3_B2;
-- Node name is '|SRAMCONTROLLER:1|~276~1'
-- Equation name is '_LC7_B2', type is buried
-- synthesized logic cell
_LC7_B2 = LCELL( _EQ046);
_EQ046 = !_LC1_B2 & _LC1_B4 & !_LC2_B2 & _LC3_B2;
-- Node name is '|SRAMCONTROLLER:1|:276'
-- Equation name is '_LC5_B2', type is buried
!_LC5_B2 = _LC5_B2~NOT;
_LC5_B2~NOT = LCELL( _EQ047);
_EQ047 = _LC3_B2
# !_LC1_B4
# _LC1_B2
# _LC2_B2;
-- Node name is '|SRAMCONTROLLER:1|:303'
-- Equation name is '_LC4_B12', type is buried
_LC4_B12 = LCELL( _EQ048);
_EQ048 = _LC1_B2 & !_LC1_B4 & !_LC2_B2 & !_LC3_B2;
-- Node name is '|SRAMCONTROLLER:1|~747~1'
-- Equation name is '_LC6_B12', type is buried
-- synthesized logic cell
_LC6_B12 = LCELL( _EQ049);
_EQ049 = !_LC2_B12 & _LC4_B12
# _LC4_B12 & !_LC8_B12;
-- Node name is '|SRAMCONTROLLER:1|~770~1'
-- Equation name is '_LC7_B12', type is buried
-- synthesized logic cell
_LC7_B12 = LCELL( _EQ050);
_EQ050 = _LC4_B12 & !_LC8_B12
# _LC4_B2;
-- Node name is '|SRAMCONTROLLER:1|~788~1'
-- Equation name is '_LC5_B12', type is buried
-- synthesized logic cell
_LC5_B12 = LCELL( _EQ051);
_EQ051 = !_LC3_B12 & _LC6_B12
# _LC4_B2;
-- Node name is '|SRAMCONTROLLER:1|~806~1'
-- Equation name is '_LC7_B19', type is buried
-- synthesized logic cell
_LC7_B19 = LCELL( _EQ052);
_EQ052 = _LC6_B12 & !_LC8_B19
# _LC4_B2;
-- Node name is '|SRAMCONTROLLER:1|~824~1'
-- Equation name is '_LC4_B19', type is buried
-- synthesized logic cell
_LC4_B19 = LCELL( _EQ053);
_EQ053 = !_LC2_B19 & _LC6_B12
# _LC4_B2;
-- Node name is '|SRAMCONTROLLER:1|~842~1'
-- Equation name is '_LC3_B19', type is buried
-- synthesized logic cell
_LC3_B19 = LCELL( _EQ054);
_EQ054 = _LC6_B12 & !_LC8_B15
# _LC4_B2;
-- Node name is '|SRAMCONTROLLER:1|~860~1'
-- Equation name is '_LC7_B15', type is buried
-- synthesized logic cell
_LC7_B15 = LCELL( _EQ055);
_EQ055 = !_LC4_B15 & _LC6_B12
# _LC4_B2;
-- Node name is '|SRAMCONTROLLER:1|~878~1'
-- Equation name is '_LC5_B15', type is buried
-- synthesized logic cell
_LC5_B15 = LCELL( _EQ056);
_EQ056 = !_LC3_B15 & _LC6_B12
# _LC4_B2;
-- Node name is '|SRAMCONTROLLER:1|~896~1'
-- Equation name is '_LC2_B17', type is buried
-- synthesized logic cell
_LC2_B17 = LCELL( _EQ057);
_EQ057 = _LC6_B12 & !_LC8_B17
# _LC4_B2;
-- Node name is '|SRAMCONTROLLER:1|~914~1'
-- Equation name is '_LC6_B17', type is buried
-- synthesized logic cell
_LC6_B17 = LCELL( _EQ058);
_EQ058 = !_LC1_B17 & _LC6_B12
# _LC4_B2;
-- Node name is '|SRAMCONTROLLER:1|~932~1'
-- Equation name is '_LC4_B17', type is buried
-- synthesized logic cell
_LC4_B17 = LCELL( _EQ059);
_EQ059 = !_LC5_B17 & _LC6_B12
# _LC4_B2;
-- Node name is '|SRAMCONTROLLER:1|~950~1'
-- Equation name is '_LC4_B2', type is buried
-- synthesized logic cell
!_LC4_B2 = _LC4_B2~NOT;
_LC4_B2~NOT = LCELL( _EQ060);
_EQ060 = _LC1_B2 & !_LC1_B4 & !_LC2_B2 & !_LC3_B2;
-- Node name is '|SRAMCONTROLLER:1|~1112~1'
-- Equation name is '_LC8_B2', type is buried
-- synthesized logic cell
_LC8_B2 = LCELL( _EQ061);
_EQ061 = _LC1_B2
# _LC2_B2
# _LC1_B4
# !_LC3_B2;
Project Informatione:\my documents\my_vhdl\sram_controller\srm_read_and_write.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,804K
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