parallel_crc.vhd

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-- Design Name : parallel_crc_ccitt
-- File Name   : parallel_crc.vhd
-- Function    : CCITT Parallel CRC
-- Coder       : Deepak Kumar Tala (Verilog)
-- Translator  : Alexander H Pham (VHDL)
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library ieee;
    use ieee.std_logic_1164.all;

entity parallel_crc_ccitt is
    port (
        clk     :in  std_logic;
        reset   :in  std_logic;
        enable  :in  std_logic;
        init    :in  std_logic;
        data_in :in  std_logic_vector (7 downto 0);
        crc_out :out std_logic_vector (15 downto 0)
    );
end entity;

architecture rtl of parallel_crc_ccitt is
    signal crc_reg  :std_logic_vector (15 downto 0);
    signal next_crc :std_logic_vector (15 downto 0);
begin

    crc_out <= crc_reg;
    
    -- CRC Control logic
    process (clk) begin
        if (rising_edge(clk)) then
            if (reset = '1') then
                crc_reg <= x"FFFF";
            elsif (enable = '1') then
                if (init = '1') then
                    crc_reg <= x"FFFF";
                else
                    crc_reg <= next_crc;
                end if;
            end if;
        end if;
    end process;
    
    -- Parallel CRC calculation
    next_crc(0)  <= data_in(7) xor data_in(0) xor crc_reg(4) 
                    xor crc_reg(11);
    next_crc(1)  <= data_in(1) xor crc_reg(5);
    next_crc(2)  <= data_in(2) xor crc_reg(6);
    next_crc(3)  <= data_in(3) xor crc_reg(7);
    next_crc(4)  <= data_in(7) xor data_in(5) xor data_in(0) 
                    xor crc_reg(4) xor crc_reg(9) xor crc_reg(11);
    next_crc(6)  <= data_in(6) xor data_in(1) xor crc_reg(5) 
                    xor crc_reg(10);
    next_crc(7)  <= data_in(7) xor data_in(2) xor crc_reg(6) 
                    xor crc_reg(11);
    next_crc(8)  <= data_in(3) xor crc_reg(0) xor crc_reg(7);
    next_crc(9)  <= data_in(4) xor crc_reg(1) xor crc_reg(8);
    next_crc(10) <= data_in(5) xor crc_reg(2) xor crc_reg(9);
    next_crc(11) <= data_in(6) xor crc_reg(3) xor crc_reg(10);
end architecture;