prev_cmp_oscillograph.tan.qmsg

在EP1C6Q240上实现示波器的逻辑代码.Verilog编写!很好用.调试成功.

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "PLL:PLL\|altpll:altpll_component\|_clk0 register trigger~reg0 register trigger~reg0 1.276 ns " "Info: Minimum slack time is 1.276 ns for clock \"PLL:PLL\|altpll:altpll_component\|_clk0\" between source register \"trigger~reg0\" and destination register \"trigger~reg0\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.067 ns + Shortest register register " "Info: + Shortest register to register delay is 1.067 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns trigger~reg0 1 REG LC_X24_Y7_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y7_N2; Fanout = 6; REG Node = 'trigger~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { trigger~reg0 } "NODE_NAME" } } { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.589 ns) + CELL(0.478 ns) 1.067 ns trigger~reg0 2 REG LC_X24_Y7_N2 6 " "Info: 2: + IC(0.589 ns) + CELL(0.478 ns) = 1.067 ns; Loc. = LC_X24_Y7_N2; Fanout = 6; REG Node = 'trigger~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.067 ns" { trigger~reg0 trigger~reg0 } "NODE_NAME" } } { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns ( 44.80 % ) " "Info: Total cell delay = 0.478 ns ( 44.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.589 ns ( 55.20 % ) " "Info: Total interconnect delay = 0.589 ns ( 55.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.067 ns" { trigger~reg0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.067 ns" { trigger~reg0 {} trigger~reg0 {} } { 0.000ns 0.589ns } { 0.000ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.885 ns " "Info: + Latch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLL:PLL\|altpll:altpll_component\|_clk0 5.000 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"PLL:PLL\|altpll:altpll_component\|_clk0\" is 5.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL:PLL\|altpll:altpll_component\|_clk0 5.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"PLL:PLL\|altpll:altpll_component\|_clk0\" is 5.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:PLL\|altpll:altpll_component\|_clk0 destination 2.352 ns + Longest register " "Info: + Longest clock path from clock \"PLL:PLL\|altpll:altpll_component\|_clk0\" to destination register is 2.352 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:PLL\|altpll:altpll_component\|_clk0 1 CLK PLL_2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 2; CLK Node = 'PLL:PLL\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL:PLL|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.641 ns) + CELL(0.711 ns) 2.352 ns trigger~reg0 2 REG LC_X24_Y7_N2 6 " "Info: 2: + IC(1.641 ns) + CELL(0.711 ns) = 2.352 ns; Loc. = LC_X24_Y7_N2; Fanout = 6; REG Node = 'trigger~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.23 % ) " "Info: Total cell delay = 0.711 ns ( 30.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.641 ns ( 69.77 % ) " "Info: Total interconnect delay = 1.641 ns ( 69.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:PLL\|altpll:altpll_component\|_clk0 source 2.352 ns - Shortest register " "Info: - Shortest clock path from clock \"PLL:PLL\|altpll:altpll_component\|_clk0\" to source register is 2.352 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:PLL\|altpll:altpll_component\|_clk0 1 CLK PLL_2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 2; CLK Node = 'PLL:PLL\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL:PLL|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.641 ns) + CELL(0.711 ns) 2.352 ns trigger~reg0 2 REG LC_X24_Y7_N2 6 " "Info: 2: + IC(1.641 ns) + CELL(0.711 ns) = 2.352 ns; Loc. = LC_X24_Y7_N2; Fanout = 6; REG Node = 'trigger~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.23 % ) " "Info: Total cell delay = 0.711 ns ( 30.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.641 ns ( 69.77 % ) " "Info: Total interconnect delay = 1.641 ns ( 69.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.067 ns" { trigger~reg0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.067 ns" { trigger~reg0 {} trigger~reg0 {} } { 0.000ns 0.589ns } { 0.000ns 0.478ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "inclk register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|base_address\[0\] register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|base_address\[0\] 822 ps " "Info: Minimum slack time is 822 ps for clock \"inclk\" between source register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|base_address\[0\]\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|base_address\[0\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.613 ns + Shortest register register " "Info: + Shortest register to register delay is 0.613 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|base_address\[0\] 1 REG LC_X19_Y8_N0 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y8_N0; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|base_address\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0] } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.613 ns) 0.613 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|base_address\[0\] 2 REG LC_X19_Y8_N0 3 " "Info: 2: + IC(0.000 ns) + CELL(0.613 ns) = 0.613 ns; Loc. = LC_X19_Y8_N0; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|base_address\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.613 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0] } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.613 ns ( 100.00 % ) " "Info: Total cell delay = 0.613 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.613 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0] sld_signaltap:auto