prev_cmp_oscillograph.tan.qmsg

在EP1C6Q240上实现示波器的逻辑代码.Verilog编写!很好用.调试成功.

{ "Info" "ITDB_FULL_SLACK_RESULT" "PLL:PLL\|altpll:altpll_component\|_clk0 register trigger~reg0 register trigger~reg0 3.672 ns " "Info: Slack time is 3.672 ns for clock \"PLL:PLL\|altpll:altpll_component\|_clk0\" between source register \"trigger~reg0\" and destination register \"trigger~reg0\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" {  } {  } 0 0 "Fmax is restricted to %1!s! due to tcl and tch limits" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "4.739 ns + Largest register register " "Info: + Largest register to register requirement is 4.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.000 ns + " "Info: + Setup relationship between source and destination is 5.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 3.115 ns " "Info: + Latch edge is 3.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLL:PLL\|altpll:altpll_component\|_clk0 5.000 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"PLL:PLL\|altpll:altpll_component\|_clk0\" is 5.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL:PLL\|altpll:altpll_component\|_clk0 5.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"PLL:PLL\|altpll:altpll_component\|_clk0\" is 5.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:PLL\|altpll:altpll_component\|_clk0 destination 2.352 ns + Shortest register " "Info: + Shortest clock path from clock \"PLL:PLL\|altpll:altpll_component\|_clk0\" to destination register is 2.352 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:PLL\|altpll:altpll_component\|_clk0 1 CLK PLL_2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 2; CLK Node = 'PLL:PLL\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL:PLL|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.641 ns) + CELL(0.711 ns) 2.352 ns trigger~reg0 2 REG LC_X24_Y7_N2 6 " "Info: 2: + IC(1.641 ns) + CELL(0.711 ns) = 2.352 ns; Loc. = LC_X24_Y7_N2; Fanout = 6; REG Node = 'trigger~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.23 % ) " "Info: Total cell delay = 0.711 ns ( 30.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.641 ns ( 69.77 % ) " "Info: Total interconnect delay = 1.641 ns ( 69.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:PLL\|altpll:altpll_component\|_clk0 source 2.352 ns - Longest register " "Info: - Longest clock path from clock \"PLL:PLL\|altpll:altpll_component\|_clk0\" to source register is 2.352 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:PLL\|altpll:altpll_component\|_clk0 1 CLK PLL_2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 2; CLK Node = 'PLL:PLL\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL:PLL|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.641 ns) + CELL(0.711 ns) 2.352 ns trigger~reg0 2 REG LC_X24_Y7_N2 6 " "Info: 2: + IC(1.641 ns) + CELL(0.711 ns) = 2.352 ns; Loc. = LC_X24_Y7_N2; Fanout = 6; REG Node = 'trigger~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.23 % ) " "Info: Total cell delay = 0.711 ns ( 30.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.641 ns ( 69.77 % ) " "Info: Total interconnect delay = 1.641 ns ( 69.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.067 ns - Longest register register " "Info: - Longest register to register delay is 1.067 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns trigger~reg0 1 REG LC_X24_Y7_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y7_N2; Fanout = 6; REG Node = 'trigger~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { trigger~reg0 } "NODE_NAME" } } { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.589 ns) + CELL(0.478 ns) 1.067 ns trigger~reg0 2 REG LC_X24_Y7_N2 6 " "Info: 2: + IC(0.589 ns) + CELL(0.478 ns) = 1.067 ns; Loc. = LC_X24_Y7_N2; Fanout = 6; REG Node = 'trigger~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.067 ns" { trigger~reg0 trigger~reg0 } "NODE_NAME" } } { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns ( 44.80 % ) " "Info: Total cell delay = 0.478 ns ( 44.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.589 ns ( 55.20 % ) " "Info: Total interconnect delay = 0.589 ns ( 55.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.067 ns" { trigger~reg0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.067 ns" { trigger~reg0 {} trigger~reg0 {} } { 0.000ns 0.589ns } { 0.000ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.067 ns" { trigger~reg0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.067 ns" { trigger~reg0 {} trigger~reg0 {} } { 0.000ns 0.589ns } { 0.000ns 0.478ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "inclk register trigger~reg0 register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[1\] 1.471 ns " "Info: Slack time is 1.471 ns for clock \"inclk\" between source register \"trigger~reg0\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[1\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "2.181 ns + Largest register register " "Info: + Largest register to register requirement is 2.181 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "1.885 ns + " "Info: + Setup relationship between source and destination is 1.885 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination inclk 25.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"inclk\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 3.115 ns " "Info: - Launch edge is 3.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL:PLL\|altpll:altpll_component\|_clk0 5.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"PLL:PLL\|altpll:altpll_component\|_clk0\" is 5.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.557 ns + Largest " "Info: + Largest clock skew is 0.557 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk destination 2.909 ns + Shortest register " "Info: + Shortest clock path from clock \"inclk\" to destination register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns inclk 1 CLK PIN_153 178 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 178; CLK Node = 'inclk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.711 ns) 2.909 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[1\] 2 REG LC_X24_Y7_N6 3 " "Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X24_Y7_N6; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.440 ns" { inclk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 939 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.94 % ) " "Info: Total cell delay = 2.180 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { inclk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { inclk {} inclk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] {} } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:PLL\|altpll:altpll_component\|_clk0 source 2.352 ns - Longest register " "Info: - Longest clock path from clock \"PLL:PLL\|altpll:altpll_component\|_clk0\" to source register is 2.352 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:PLL\|altpll:altpll_component\|_clk0 1 CLK PLL_2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 2; CLK Node = 'PLL:PLL\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL:PLL|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.641 ns) + CELL(0.711 ns) 2.352 ns trigger~reg0 2 REG LC_X24_Y7_N2 6 " "Info: 2: + IC(1.641 ns) + CELL(0.711 ns) = 2.352 ns; Loc. = LC_X24_Y7_N2; Fanout = 6; REG Node = 'trigger~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.23 % ) " "Info: Total cell delay = 0.711 ns ( 30.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.641 ns ( 69.77 % ) " "Info: Total interconnect delay = 1.641 ns ( 69.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { inclk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { inclk {} inclk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] {} } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 939 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { inclk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { inclk {} inclk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] {} } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.710 ns - Longest register register " "Info: - Longest register to register delay is 0.710 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns trigger~reg0 1 REG LC_X24_Y7_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y7_N2; Fanout = 6; REG Node = 'trigger~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { trigger~reg0 } "NODE_NAME" } } { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.595 ns) + CELL(0.115 ns) 0.710 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[1\] 2 REG LC_X24_Y7_N6 3 " "Info: 2: + IC(0.595 ns) + CELL(0.115 ns) = 0.710 ns; Loc. = LC_X24_Y7_N6; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.710 ns" { trigger~reg0 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 939 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 16.20 % ) " "Info: Total cell delay = 0.115 ns ( 16.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.595 ns ( 83.80 % ) " "Info: Total interconnect delay = 0.595 ns ( 83.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.710 ns" { trigger~reg0 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.710 ns" { trigger~reg0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] {} } { 0.000ns 0.595ns } { 0.000ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { inclk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { inclk {} inclk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] {} } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 trigger~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { PLL:PLL|altpll:altpll_component|_clk0 {} trigger~reg0 {} } { 0.000ns 1.641ns } { 0.000ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.710 ns" { trigger~reg0 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.710 ns" { trigger~reg0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] {} } { 0.000ns 0.595ns } { 0.000ns 0.115ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] register sld_hub:sld_hub_inst\|hub_tdo_reg 60.75 MHz 16.462 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 60.75 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 16.462 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.970 ns + Longest register register " "Info: + Longest register to register delay is 7.970 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] 1 REG LC_X13_Y10_N2 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y10_N2; Fanout = 12; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.317 ns) + CELL(0.292 ns) 1.609 ns sld_hub:sld_hub_inst\|node_ena~10 2 COMB LC_X14_Y9_N8 5 " "Info: 2: + IC(1.317 ns) + CELL(0.292 ns) = 1.609 ns; Loc. = LC_X14_Y9_N8; Fanout = 5; COMB Node = 'sld_hub:sld_hub_inst\|node_ena~10'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.609 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] sld_hub:sld_hub_inst|node_ena~10 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.474 ns) + CELL(0.292 ns) 2.375 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~31 3 COMB LC_X14_Y9_N6 7 " "Info: 3: + IC(0.474 ns) + CELL(0.292 ns) = 2.375 ns; Loc. = LC_X14_Y9_N6; Fanout = 7; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~31'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.766 ns" { sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 803 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.671 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~68 4 COMB LC_X14_Y9_N7 18 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 2.671 ns; Loc. = LC_X14_Y9_N7; Fanout = 18; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~68'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~68 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 831 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.262 ns) + CELL(0.292 ns) 4.225 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~425 5 COMB LC_X15_Y8_N4 1 " "Info: 5: + IC(1.262 ns) + CELL(0.292 ns) = 4.225 ns; Loc. = LC_X15_Y8_N4; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~425'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.554 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~68 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.405 ns) + CELL(0.442 ns) 5.072 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~428 6 COMB LC_X15_Y8_N2 1 " "Info: 6: + IC(0.405 ns) + CELL(0.442 ns) = 5.072 ns; Loc. = LC_X15_Y8_N2; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~428'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.847 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.590 ns) 6.089 ns sld_hub:sld_hub_inst\|hub_tdo_reg~294 7 COMB LC_X15_Y8_N1 1 " "Info: 7: + IC(0.427 ns) + CELL(0.590 ns) = 6.089 ns; Loc. = LC_X15_Y8_N1; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~294'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.017 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.572 ns) + CELL(0.309 ns) 7.970 ns sld_hub:sld_hub_inst\|hub_tdo_reg 8 REG LC_X11_Y10_N9 2 " "Info: 8: + IC(1.572 ns) + CELL(0.309 ns) = 7.970 ns; Loc. = LC_X11_Y10_N9; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.881 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.331 ns ( 29.25 % ) " "Info: Total cell delay = 2.331 ns ( 29.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.639 ns ( 70.75 % ) " "Info: Total interconnect delay = 5.639 ns ( 70.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.970 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~68 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.970 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} sld_hub:sld_hub_inst|node_ena~10 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~68 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 {} sld_hub:sld_hub_inst|hub_tdo_reg~294 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 1.317ns 0.474ns 0.182ns 1.262ns 0.405ns 0.427ns 1.572ns } { 0.000ns 0.292ns 0.292ns 0.114ns 0.292ns 0.442ns 0.590ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.292 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 238 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 238; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.581 ns) + CELL(0.711 ns) 5.292 ns sld_hub:sld_hub_inst\|hub_tdo_reg 2 REG LC_X11_Y10_N9 2 " "Info: 2: + IC(4.581 ns) + CELL(0.711 ns) = 5.292 ns; Loc. = LC_X11_Y10_N9; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.44 % ) " "Info: Total cell delay = 0.711 ns ( 13.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.581 ns ( 86.56 % ) " "Info: Total interconnect delay = 4.581 ns ( 86.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.581ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.292 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 238 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 238; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.581 ns) + CELL(0.711 ns) 5.292 ns sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] 2 REG LC_X13_Y10_N2 12 " "Info: 2: + IC(4.581 ns) + CELL(0.711 ns) = 5.292 ns; Loc. = LC_X13_Y10_N2; Fanout = 12; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.44 % ) " "Info: Total cell delay = 0.711 ns ( 13.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.581 ns ( 86.56 % ) " "Info: Total interconnect delay = 4.581 ns ( 86.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} } { 0.000ns 4.581ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.581ns } { 0.000ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} } { 0.000ns 4.581ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.970 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~68 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.970 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} sld_hub:sld_hub_inst|node_ena~10 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~68 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 {} sld_hub:sld_hub_inst|hub_tdo_reg~294 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 1.317ns 0.474ns 0.182ns 1.262ns 0.405ns 0.427ns 1.572ns } { 0.000ns 0.292ns 0.292ns 0.114ns 0.292ns 0.442ns 0.590ns 0.309ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.581ns } { 0.000ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} } { 0.000ns 4.581ns } { 0.000ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}