i2c.map.qmsg

I2C总线的逻辑代码.Verilog编写!很好用.调试成功.

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_clk i2c_clk:U3 " "Info: Elaborating entity \"i2c_clk\" for hierarchy \"i2c_clk:U3\"" {  } { { "MyDD/i2c.v" "U3" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 169 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c_clk.v(79) " "Warning (10230): Verilog HDL assignment warning at i2c_clk.v(79): truncated value with size 32 to match size of target (8)" {  } { { "MyDD/i2c_clk.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_clk.v" 79 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_st i2c_st:U4 " "Info: Elaborating entity \"i2c_st\" for hierarchy \"i2c_st:U4\"" {  } { { "MyDD/i2c.v" "U4" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 184 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 i2c_st.v(184) " "Warning (10230): Verilog HDL assignment warning at i2c_st.v(184): truncated value with size 32 to match size of target (3)" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 184 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_tbuf i2c_tbuf:U5 " "Info: Elaborating entity \"i2c_tbuf\" for hierarchy \"i2c_tbuf:U5\"" {  } { { "MyDD/i2c.v" "U5" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 194 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|i2c\|i2c_st:U4\|i2c_state 15 " "Info: State machine \"\|i2c\|i2c_st:U4\|i2c_state\" contains 15 states" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|i2c\|i2c_st:U4\|i2c_state " "Info: Selected Auto state machine encoding method for state machine \"\|i2c\|i2c_st:U4\|i2c_state\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|i2c\|i2c_st:U4\|i2c_state " "Info: Encoding result for state machine \"\|i2c\|i2c_st:U4\|i2c_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "15 " "Info: Completed encoding using 15 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.dis_clk1 " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.dis_clk1\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.stop1 " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.stop1\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.start2 " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.start2\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.start1 " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.start1\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.data " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.data\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.w_add " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.w_add\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.dev_add2 " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.dev_add2\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.dev_add1 " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.dev_add1\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.ack4 " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.ack4\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.ack3 " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.ack3\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.ack2 " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.ack2\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.ack1 " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.ack1\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.wait1 " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.wait1\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.en_clk " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.en_clk\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_st:U4\|i2c_state.idle " "Info: Encoded state bit \"i2c_st:U4\|i2c_state.idle\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.idle 000000000000000 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.idle\" uses code string \"000000000000000\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.en_clk 000000000000011 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.en_clk\" uses code string \"000000000000011\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.wait1 000000000000101 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.wait1\" uses code string \"000000000000101\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.ack1 000000000001001 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.ack1\" uses code string \"000000000001001\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.ack2 000000000010001 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.ack2\" uses code string \"000000000010001\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.ack3 000000000100001 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.ack3\" uses code string \"000000000100001\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.ack4 000000001000001 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.ack4\" uses code string \"000000001000001\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.dev_add1 000000010000001 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.dev_add1\" uses code string \"000000010000001\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.dev_add2 000000100000001 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.dev_add2\" uses code string \"000000100000001\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.w_add 000001000000001 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.w_add\" uses code string \"000001000000001\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.data 000010000000001 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.data\" uses code string \"000010000000001\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.start1 000100000000001 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.start1\" uses code string \"000100000000001\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.start2 001000000000001 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.start2\" uses code string \"001000000000001\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.stop1 010000000000001 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.stop1\" uses code string \"010000000000001\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_st:U4\|i2c_state.dis_clk1 100000000000001 " "Info: State \"\|i2c\|i2c_st:U4\|i2c_state.dis_clk1\" uses code string \"100000000000001\"" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 88 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "MyDD/i2c_wreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_wreg.v" 73 -1 0 } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 72 -1 0 } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 71 -1 0 } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 183 -1 0 } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 183 -1 0 } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 183 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "4 4 " "Info: 4 registers lost all their fanouts during netlist optimizations. The first 4 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "i2c_st:U4\|i2c_state~88 " "Info: Register \"i2c_st:U4\|i2c_state~88\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "i2c_st:U4\|i2c_state~89 " "Info: Register \"i2c_st:U4\|i2c_state~89\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "i2c_st:U4\|i2c_state~90 " "Info: Register \"i2c_st:U4\|i2c_state~90\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "i2c_st:U4\|i2c_state~91 " "Info: Register \"i2c_st:U4\|i2c_state~91\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "115 " "Info: Implemented 115 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "9 " "Info: Implemented 9 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "96 " "Info: Implemented 96 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/Study FPGA/I2C/i2c.map.smsg " "Info: Generated suppressed messages file E:/Study FPGA/I2C/i2c.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "142 " "Info: Allocated 142 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 04 20:19:31 2008 " "Info: Processing ended: Fri Apr 04 20:19:31 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}