i2c.tan.qmsg

I2C总线的逻辑代码.Verilog编写!很好用.调试成功.

{ "Info" "ITDB_FULL_TPD_RESULT" "addr\[0\] data\[7\] 15.271 ns Longest " "Info: Longest tpd from source pin \"addr\[0\]\" to destination pin \"data\[7\]\" is 15.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns addr\[0\] 1 PIN PIN_21 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_21; Fanout = 9; PIN Node = 'addr\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr[0] } "NODE_NAME" } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.854 ns) + CELL(0.114 ns) 9.437 ns i2c_rreg:U2\|Mux0~127 2 COMB LC_X31_Y15_N4 1 " "Info: 2: + IC(7.854 ns) + CELL(0.114 ns) = 9.437 ns; Loc. = LC_X31_Y15_N4; Fanout = 1; COMB Node = 'i2c_rreg:U2\|Mux0~127'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.968 ns" { addr[0] i2c_rreg:U2|Mux0~127 } "NODE_NAME" } } { "MyDD/i2c_rreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_rreg.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.472 ns) + CELL(0.114 ns) 11.023 ns i2c_rreg:U2\|Mux0~128 3 COMB LC_X33_Y14_N1 1 " "Info: 3: + IC(1.472 ns) + CELL(0.114 ns) = 11.023 ns; Loc. = LC_X33_Y14_N1; Fanout = 1; COMB Node = 'i2c_rreg:U2\|Mux0~128'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.586 ns" { i2c_rreg:U2|Mux0~127 i2c_rreg:U2|Mux0~128 } "NODE_NAME" } } { "MyDD/i2c_rreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_rreg.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.140 ns) + CELL(2.108 ns) 15.271 ns data\[7\] 4 PIN PIN_186 0 " "Info: 4: + IC(2.140 ns) + CELL(2.108 ns) = 15.271 ns; Loc. = PIN_186; Fanout = 0; PIN Node = 'data\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.248 ns" { i2c_rreg:U2|Mux0~128 data[7] } "NODE_NAME" } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.805 ns ( 24.92 % ) " "Info: Total cell delay = 3.805 ns ( 24.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.466 ns ( 75.08 % ) " "Info: Total interconnect delay = 11.466 ns ( 75.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.271 ns" { addr[0] i2c_rreg:U2|Mux0~127 i2c_rreg:U2|Mux0~128 data[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.271 ns" { addr[0] {} addr[0]~out0 {} i2c_rreg:U2|Mux0~127 {} i2c_rreg:U2|Mux0~128 {} data[7] {} } { 0.000ns 0.000ns 7.854ns 1.472ns 2.140ns } { 0.000ns 1.469ns 0.114ns 0.114ns 2.108ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "i2c_wreg:U1\|wrd_add\[6\] data\[6\] reg_clk_in -3.579 ns register " "Info: th for register \"i2c_wreg:U1\|wrd_add\[6\]\" (data pin = \"data\[6\]\", clock pin = \"reg_clk_in\") is -3.579 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "reg_clk_in destination 2.962 ns + Longest register " "Info: + Longest clock path from clock \"reg_clk_in\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reg_clk_in 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'reg_clk_in'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reg_clk_in } "NODE_NAME" } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns i2c_wreg:U1\|wrd_add\[6\] 2 REG LC_X31_Y15_N2 2 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y15_N2; Fanout = 2; REG Node = 'i2c_wreg:U1\|wrd_add\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { reg_clk_in i2c_wreg:U1|wrd_add[6] } "NODE_NAME" } } { "MyDD/i2c_wreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_wreg.v" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { reg_clk_in i2c_wreg:U1|wrd_add[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { reg_clk_in {} reg_clk_in~out0 {} i2c_wreg:U1|wrd_add[6] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "MyDD/i2c_wreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_wreg.v" 104 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.556 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.556 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data\[6\] 1 PIN PIN_162 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_162; Fanout = 1; PIN Node = 'data\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[6] } "NODE_NAME" } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns data\[6\]~1 2 COMB IOC_X35_Y15_N2 1 " "Info: 2: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = IOC_X35_Y15_N2; Fanout = 1; COMB Node = 'data\[6\]~1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.469 ns" { data[6] data[6]~1 } "NODE_NAME" } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.972 ns) + CELL(0.115 ns) 6.556 ns i2c_wreg:U1\|wrd_add\[6\] 3 REG LC_X31_Y15_N2 2 " "Info: 3: + IC(4.972 ns) + CELL(0.115 ns) = 6.556 ns; Loc. = LC_X31_Y15_N2; Fanout = 2; REG Node = 'i2c_wreg:U1\|wrd_add\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.087 ns" { data[6]~1 i2c_wreg:U1|wrd_add[6] } "NODE_NAME" } } { "MyDD/i2c_wreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_wreg.v" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 24.16 % ) " "Info: Total cell delay = 1.584 ns ( 24.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.972 ns ( 75.84 % ) " "Info: Total interconnect delay = 4.972 ns ( 75.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.556 ns" { data[6] data[6]~1 i2c_wreg:U1|wrd_add[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.556 ns" { data[6] {} data[6]~1 {} i2c_wreg:U1|wrd_add[6] {} } { 0.000ns 0.000ns 4.972ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { reg_clk_in i2c_wreg:U1|wrd_add[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { reg_clk_in {} reg_clk_in~out0 {} i2c_wreg:U1|wrd_add[6] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.556 ns" { data[6] data[6]~1 i2c_wreg:U1|wrd_add[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.556 ns" { data[6] {} data[6]~1 {} i2c_wreg:U1|wrd_add[6] {} } { 0.000ns 0.000ns 4.972ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 04 20:19:46 2008 " "Info: Processing ended: Fri Apr 04 20:19:46 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}