i2c.tan.qmsg

I2C总线的逻辑代码.Verilog编写!很好用.调试成功.

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register i2c_st:U4\|bit_cntr\[2\] register i2c_st:U4\|i2c_rdata\[5\] 245.1 MHz 4.08 ns Internal " "Info: Clock \"clock\" has Internal fmax of 245.1 MHz between source register \"i2c_st:U4\|bit_cntr\[2\]\" and destination register \"i2c_st:U4\|i2c_rdata\[5\]\" (period= 4.08 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.819 ns + Longest register register " "Info: + Longest register to register delay is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c_st:U4\|bit_cntr\[2\] 1 REG LC_X31_Y13_N1 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y13_N1; Fanout = 13; REG Node = 'i2c_st:U4\|bit_cntr\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_st:U4|bit_cntr[2] } "NODE_NAME" } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.370 ns) + CELL(0.590 ns) 1.960 ns i2c_st:U4\|i2c_rdata~1775 2 COMB LC_X32_Y14_N3 1 " "Info: 2: + IC(1.370 ns) + CELL(0.590 ns) = 1.960 ns; Loc. = LC_X32_Y14_N3; Fanout = 1; COMB Node = 'i2c_st:U4\|i2c_rdata~1775'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.960 ns" { i2c_st:U4|bit_cntr[2] i2c_st:U4|i2c_rdata~1775 } "NODE_NAME" } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.121 ns) + CELL(0.738 ns) 3.819 ns i2c_st:U4\|i2c_rdata\[5\] 3 REG LC_X30_Y14_N5 2 " "Info: 3: + IC(1.121 ns) + CELL(0.738 ns) = 3.819 ns; Loc. = LC_X30_Y14_N5; Fanout = 2; REG Node = 'i2c_st:U4\|i2c_rdata\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.859 ns" { i2c_st:U4|i2c_rdata~1775 i2c_st:U4|i2c_rdata[5] } "NODE_NAME" } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 262 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.328 ns ( 34.77 % ) " "Info: Total cell delay = 1.328 ns ( 34.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.491 ns ( 65.23 % ) " "Info: Total interconnect delay = 2.491 ns ( 65.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { i2c_st:U4|bit_cntr[2] i2c_st:U4|i2c_rdata~1775 i2c_st:U4|i2c_rdata[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { i2c_st:U4|bit_cntr[2] {} i2c_st:U4|i2c_rdata~1775 {} i2c_st:U4|i2c_rdata[5] {} } { 0.000ns 1.370ns 1.121ns } { 0.000ns 0.590ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 46 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 46; CLK Node = 'clock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns i2c_st:U4\|i2c_rdata\[5\] 2 REG LC_X30_Y14_N5 2 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X30_Y14_N5; Fanout = 2; REG Node = 'i2c_st:U4\|i2c_rdata\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clock i2c_st:U4|i2c_rdata[5] } "NODE_NAME" } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 262 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clock i2c_st:U4|i2c_rdata[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clock {} clock~out0 {} i2c_st:U4|i2c_rdata[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.962 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 46 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 46; CLK Node = 'clock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns i2c_st:U4\|bit_cntr\[2\] 2 REG LC_X31_Y13_N1 13 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y13_N1; Fanout = 13; REG Node = 'i2c_st:U4\|bit_cntr\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clock i2c_st:U4|bit_cntr[2] } "NODE_NAME" } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clock i2c_st:U4|bit_cntr[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clock {} clock~out0 {} i2c_st:U4|bit_cntr[2] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clock i2c_st:U4|i2c_rdata[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clock {} clock~out0 {} i2c_st:U4|i2c_rdata[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clock i2c_st:U4|bit_cntr[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clock {} clock~out0 {} i2c_st:U4|bit_cntr[2] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 183 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 262 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { i2c_st:U4|bit_cntr[2] i2c_st:U4|i2c_rdata~1775 i2c_st:U4|i2c_rdata[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { i2c_st:U4|bit_cntr[2] {} i2c_st:U4|i2c_rdata~1775 {} i2c_st:U4|i2c_rdata[5] {} } { 0.000ns 1.370ns 1.121ns } { 0.000ns 0.590ns 0.738ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clock i2c_st:U4|i2c_rdata[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clock {} clock~out0 {} i2c_st:U4|i2c_rdata[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clock i2c_st:U4|bit_cntr[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clock {} clock~out0 {} i2c_st:U4|bit_cntr[2] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "reg_clk_in " "Info: No valid register-to-register data paths exist for clock \"reg_clk_in\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "i2c_wreg:U1\|i2c_go addr\[0\] clock 8.182 ns register " "Info: tsu for register \"i2c_wreg:U1\|i2c_go\" (data pin = \"addr\[0\]\", clock pin = \"clock\") is 8.182 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.107 ns + Longest pin register " "Info: + Longest pin to register delay is 11.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns addr\[0\] 1 PIN PIN_21 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_21; Fanout = 9; PIN Node = 'addr\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr[0] } "NODE_NAME" } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.502 ns) + CELL(0.114 ns) 9.085 ns i2c_wreg:U1\|always0~26 2 COMB LC_X30_Y14_N4 2 " "Info: 2: + IC(7.502 ns) + CELL(0.114 ns) = 9.085 ns; Loc. = LC_X30_Y14_N4; Fanout = 2; COMB Node = 'i2c_wreg:U1\|always0~26'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.616 ns" { addr[0] i2c_wreg:U1|always0~26 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.415 ns) + CELL(0.607 ns) 11.107 ns i2c_wreg:U1\|i2c_go 3 REG LC_X32_Y13_N7 8 " "Info: 3: + IC(1.415 ns) + CELL(0.607 ns) = 11.107 ns; Loc. = LC_X32_Y13_N7; Fanout = 8; REG Node = 'i2c_wreg:U1\|i2c_go'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.022 ns" { i2c_wreg:U1|always0~26 i2c_wreg:U1|i2c_go } "NODE_NAME" } } { "MyDD/i2c_wreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_wreg.v" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.190 ns ( 19.72 % ) " "Info: Total cell delay = 2.190 ns ( 19.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.917 ns ( 80.28 % ) " "Info: Total interconnect delay = 8.917 ns ( 80.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.107 ns" { addr[0] i2c_wreg:U1|always0~26 i2c_wreg:U1|i2c_go } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.107 ns" { addr[0] {} addr[0]~out0 {} i2c_wreg:U1|always0~26 {} i2c_wreg:U1|i2c_go {} } { 0.000ns 0.000ns 7.502ns 1.415ns } { 0.000ns 1.469ns 0.114ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "MyDD/i2c_wreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_wreg.v" 72 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.962 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 46 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 46; CLK Node = 'clock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns i2c_wreg:U1\|i2c_go 2 REG LC_X32_Y13_N7 8 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X32_Y13_N7; Fanout = 8; REG Node = 'i2c_wreg:U1\|i2c_go'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clock i2c_wreg:U1|i2c_go } "NODE_NAME" } } { "MyDD/i2c_wreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_wreg.v" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clock i2c_wreg:U1|i2c_go } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clock {} clock~out0 {} i2c_wreg:U1|i2c_go {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.107 ns" { addr[0] i2c_wreg:U1|always0~26 i2c_wreg:U1|i2c_go } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.107 ns" { addr[0] {} addr[0]~out0 {} i2c_wreg:U1|always0~26 {} i2c_wreg:U1|i2c_go {} } { 0.000ns 0.000ns 7.502ns 1.415ns } { 0.000ns 1.469ns 0.114ns 0.607ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clock i2c_wreg:U1|i2c_go } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clock {} clock~out0 {} i2c_wreg:U1|i2c_go {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock data\[7\] i2c_st:U4\|i2c_rdata\[7\] 10.883 ns register " "Info: tco from clock \"clock\" to destination pin \"data\[7\]\" through register \"i2c_st:U4\|i2c_rdata\[7\]\" is 10.883 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.962 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 46 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 46; CLK Node = 'clock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns i2c_st:U4\|i2c_rdata\[7\] 2 REG LC_X31_Y13_N3 2 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y13_N3; Fanout = 2; REG Node = 'i2c_st:U4\|i2c_rdata\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clock i2c_st:U4|i2c_rdata[7] } "NODE_NAME" } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 262 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clock i2c_st:U4|i2c_rdata[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clock {} clock~out0 {} i2c_st:U4|i2c_rdata[7] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 262 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.697 ns + Longest register pin " "Info: + Longest register to pin delay is 7.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c_st:U4\|i2c_rdata\[7\] 1 REG LC_X31_Y13_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y13_N3; Fanout = 2; REG Node = 'i2c_st:U4\|i2c_rdata\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_st:U4|i2c_rdata[7] } "NODE_NAME" } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 262 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.273 ns) + CELL(0.590 ns) 1.863 ns i2c_rreg:U2\|Mux0~127 2 COMB LC_X31_Y15_N4 1 " "Info: 2: + IC(1.273 ns) + CELL(0.590 ns) = 1.863 ns; Loc. = LC_X31_Y15_N4; Fanout = 1; COMB Node = 'i2c_rreg:U2\|Mux0~127'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.863 ns" { i2c_st:U4|i2c_rdata[7] i2c_rreg:U2|Mux0~127 } "NODE_NAME" } } { "MyDD/i2c_rreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_rreg.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.472 ns) + CELL(0.114 ns) 3.449 ns i2c_rreg:U2\|Mux0~128 3 COMB LC_X33_Y14_N1 1 " "Info: 3: + IC(1.472 ns) + CELL(0.114 ns) = 3.449 ns; Loc. = LC_X33_Y14_N1; Fanout = 1; COMB Node = 'i2c_rreg:U2\|Mux0~128'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.586 ns" { i2c_rreg:U2|Mux0~127 i2c_rreg:U2|Mux0~128 } "NODE_NAME" } } { "MyDD/i2c_rreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_rreg.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.140 ns) + CELL(2.108 ns) 7.697 ns data\[7\] 4 PIN PIN_186 0 " "Info: 4: + IC(2.140 ns) + CELL(2.108 ns) = 7.697 ns; Loc. = PIN_186; Fanout = 0; PIN Node = 'data\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.248 ns" { i2c_rreg:U2|Mux0~128 data[7] } "NODE_NAME" } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.812 ns ( 36.53 % ) " "Info: Total cell delay = 2.812 ns ( 36.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.885 ns ( 63.47 % ) " "Info: Total interconnect delay = 4.885 ns ( 63.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.697 ns" { i2c_st:U4|i2c_rdata[7] i2c_rreg:U2|Mux0~127 i2c_rreg:U2|Mux0~128 data[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.697 ns" { i2c_st:U4|i2c_rdata[7] {} i2c_rreg:U2|Mux0~127 {} i2c_rreg:U2|Mux0~128 {} data[7] {} } { 0.000ns 1.273ns 1.472ns 2.140ns } { 0.000ns 0.590ns 0.114ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clock i2c_st:U4|i2c_rdata[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clock {} clock~out0 {} i2c_st:U4|i2c_rdata[7] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.697 ns" { i2c_st:U4|i2c_rdata[7] i2c_rreg:U2|Mux0~127 i2c_rreg:U2|Mux0~128 data[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.697 ns" { i2c_st:U4|i2c_rdata[7] {} i2c_rreg:U2|Mux0~127 {} i2c_rreg:U2|Mux0~128 {} data[7] {} } { 0.000ns 1.273ns 1.472ns 2.140ns } { 0.000ns 0.590ns 0.114ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}