i2c.fit.qmsg

I2C总线的逻辑代码.Verilog编写!很好用.调试成功.

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.593 ns register register " "Info: Estimated most critical path is register to register delay of 3.593 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c_st:U4\|scl 1 REG LAB_X32_Y14 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X32_Y14; Fanout = 13; REG Node = 'i2c_st:U4\|scl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_st:U4|scl } "NODE_NAME" } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.615 ns) + CELL(0.114 ns) 0.729 ns i2c_st:U4\|always8~13 2 COMB LAB_X32_Y14 8 " "Info: 2: + IC(0.615 ns) + CELL(0.114 ns) = 0.729 ns; Loc. = LAB_X32_Y14; Fanout = 8; COMB Node = 'i2c_st:U4\|always8~13'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.729 ns" { i2c_st:U4|scl i2c_st:U4|always8~13 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.590 ns) 2.064 ns i2c_st:U4\|i2c_rdata~1777 3 COMB LAB_X31_Y13 1 " "Info: 3: + IC(0.745 ns) + CELL(0.590 ns) = 2.064 ns; Loc. = LAB_X31_Y13; Fanout = 1; COMB Node = 'i2c_st:U4\|i2c_rdata~1777'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.335 ns" { i2c_st:U4|always8~13 i2c_st:U4|i2c_rdata~1777 } "NODE_NAME" } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.220 ns) + CELL(0.309 ns) 3.593 ns i2c_st:U4\|i2c_rdata\[6\] 4 REG LAB_X30_Y14 2 " "Info: 4: + IC(1.220 ns) + CELL(0.309 ns) = 3.593 ns; Loc. = LAB_X30_Y14; Fanout = 2; REG Node = 'i2c_st:U4\|i2c_rdata\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.529 ns" { i2c_st:U4|i2c_rdata~1777 i2c_st:U4|i2c_rdata[6] } "NODE_NAME" } } { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 262 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.013 ns ( 28.19 % ) " "Info: Total cell delay = 1.013 ns ( 28.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.580 ns ( 71.81 % ) " "Info: Total interconnect delay = 2.580 ns ( 71.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.593 ns" { i2c_st:U4|scl i2c_st:U4|always8~13 i2c_st:U4|i2c_rdata~1777 i2c_st:U4|i2c_rdata[6] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X24_Y11 X35_Y21 " "Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X24_Y11 to location X35_Y21" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "i2c_tbuf:U5\|data~8 " "Info: Following pins have the same output enable: i2c_tbuf:U5\|data~8" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[1\] 3.3-V LVTTL " "Info: Type bidirectional pin data\[1\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { data[1] } } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 79 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[5\] 3.3-V LVTTL " "Info: Type bidirectional pin data\[5\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { data[5] } } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 79 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[0\] 3.3-V LVTTL " "Info: Type bidirectional pin data\[0\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { data[0] } } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 79 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[2\] 3.3-V LVTTL " "Info: Type bidirectional pin data\[2\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { data[2] } } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 79 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[4\] 3.3-V LVTTL " "Info: Type bidirectional pin data\[4\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { data[4] } } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 79 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[6\] 3.3-V LVTTL " "Info: Type bidirectional pin data\[6\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { data[6] } } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 79 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[3\] 3.3-V LVTTL " "Info: Type bidirectional pin data\[3\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { data[3] } } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 79 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[7\] 3.3-V LVTTL " "Info: Type bidirectional pin data\[7\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { data[7] } } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 79 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "i2c_st:U4\|sda " "Info: Following pins have the same output enable: i2c_st:U4\|sda" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sda_pin 3.3-V LVTTL " "Info: Type bidirectional pin sda_pin uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { sda_pin } } } { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 95 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sda_pin } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sda_pin } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/Study FPGA/I2C/i2c.fit.smsg " "Info: Generated suppressed messages file E:/Study FPGA/I2C/i2c.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "171 " "Info: Allocated 171 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 04 20:19:38 2008 " "Info: Processing ended: Fri Apr 04 20:19:38 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}