i2c.map.rpt

I2C总线的逻辑代码.Verilog编写!很好用.调试成功.

; Parameter Settings for User Entity Instance: i2c_wreg:U1 ;
+----------------+-------+---------------------------------+
; Parameter Name ; Value ; Type                            ;
+----------------+-------+---------------------------------+
; w_add          ; 00    ; Unsigned Binary                 ;
; d_add          ; 01    ; Unsigned Binary                 ;
; s_add          ; 10    ; Unsigned Binary                 ;
+----------------+-------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------+
; Parameter Settings for User Entity Instance: i2c_rreg:U2 ;
+----------------+-------+---------------------------------+
; Parameter Name ; Value ; Type                            ;
+----------------+-------+---------------------------------+
; w_add          ; 00    ; Unsigned Binary                 ;
; d_add          ; 01    ; Unsigned Binary                 ;
; s_add          ; 10    ; Unsigned Binary                 ;
+----------------+-------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: i2c_st:U4 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; idle           ; 0000  ; Unsigned Binary               ;
; en_clk         ; 0001  ; Unsigned Binary               ;
; start1         ; 1100  ; Unsigned Binary               ;
; dev_add1       ; 1000  ; Unsigned Binary               ;
; ack1           ; 0100  ; Unsigned Binary               ;
; w_add          ; 1010  ; Unsigned Binary               ;
; ack2           ; 0101  ; Unsigned Binary               ;
; wait1          ; 0011  ; Unsigned Binary               ;
; dis_clk1       ; 1111  ; Unsigned Binary               ;
; start2         ; 1101  ; Unsigned Binary               ;
; dev_add2       ; 1001  ; Unsigned Binary               ;
; ack3           ; 0110  ; Unsigned Binary               ;
; data           ; 1011  ; Unsigned Binary               ;
; ack4           ; 0111  ; Unsigned Binary               ;
; stop1          ; 1110  ; Unsigned Binary               ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Apr 04 20:19:27 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off i2c -c i2c
Info: Found 1 design units, including 1 entities, in source file MyDD/i2c.v
    Info: Found entity 1: i2c
Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_clk.v
    Info: Found entity 1: i2c_clk
Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_rreg.v
    Info: Found entity 1: i2c_rreg
Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_st.v
    Info: Found entity 1: i2c_st
Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_tbuf.v
    Info: Found entity 1: i2c_tbuf
Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_wreg.v
    Info: Found entity 1: i2c_wreg
Info: Elaborating entity "i2c" for the top level hierarchy
Info: Elaborating entity "i2c_wreg" for hierarchy "i2c_wreg:U1"
Info: Elaborating entity "i2c_rreg" for hierarchy "i2c_rreg:U2"
Warning (10235): Verilog HDL Always Construct warning at i2c_rreg.v(86): variable "i2c_act" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at i2c_rreg.v(87): variable "i2c_act" is read inside the Always Construct but isn't in the Always Construct's Event Control
Info: Elaborating entity "i2c_clk" for hierarchy "i2c_clk:U3"
Warning (10230): Verilog HDL assignment warning at i2c_clk.v(79): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "i2c_st" for hierarchy "i2c_st:U4"
Warning (10230): Verilog HDL assignment warning at i2c_st.v(184): truncated value with size 32 to match size of target (3)
Info: Elaborating entity "i2c_tbuf" for hierarchy "i2c_tbuf:U5"
Info: State machine "|i2c|i2c_st:U4|i2c_state" contains 15 states
Info: Selected Auto state machine encoding method for state machine "|i2c|i2c_st:U4|i2c_state"
Info: Encoding result for state machine "|i2c|i2c_st:U4|i2c_state"
    Info: Completed encoding using 15 state bits
        Info: Encoded state bit "i2c_st:U4|i2c_state.dis_clk1"
        Info: Encoded state bit "i2c_st:U4|i2c_state.stop1"
        Info: Encoded state bit "i2c_st:U4|i2c_state.start2"
        Info: Encoded state bit "i2c_st:U4|i2c_state.start1"
        Info: Encoded state bit "i2c_st:U4|i2c_state.data"
        Info: Encoded state bit "i2c_st:U4|i2c_state.w_add"
        Info: Encoded state bit "i2c_st:U4|i2c_state.dev_add2"
        Info: Encoded state bit "i2c_st:U4|i2c_state.dev_add1"
        Info: Encoded state bit "i2c_st:U4|i2c_state.ack4"
        Info: Encoded state bit "i2c_st:U4|i2c_state.ack3"
        Info: Encoded state bit "i2c_st:U4|i2c_state.ack2"
        Info: Encoded state bit "i2c_st:U4|i2c_state.ack1"
        Info: Encoded state bit "i2c_st:U4|i2c_state.wait1"
        Info: Encoded state bit "i2c_st:U4|i2c_state.en_clk"
        Info: Encoded state bit "i2c_st:U4|i2c_state.idle"
    Info: State "|i2c|i2c_st:U4|i2c_state.idle" uses code string "000000000000000"
    Info: State "|i2c|i2c_st:U4|i2c_state.en_clk" uses code string "000000000000011"
    Info: State "|i2c|i2c_st:U4|i2c_state.wait1" uses code string "000000000000101"
    Info: State "|i2c|i2c_st:U4|i2c_state.ack1" uses code string "000000000001001"
    Info: State "|i2c|i2c_st:U4|i2c_state.ack2" uses code string "000000000010001"
    Info: State "|i2c|i2c_st:U4|i2c_state.ack3" uses code string "000000000100001"
    Info: State "|i2c|i2c_st:U4|i2c_state.ack4" uses code string "000000001000001"
    Info: State "|i2c|i2c_st:U4|i2c_state.dev_add1" uses code string "000000010000001"
    Info: State "|i2c|i2c_st:U4|i2c_state.dev_add2" uses code string "000000100000001"
    Info: State "|i2c|i2c_st:U4|i2c_state.w_add" uses code string "000001000000001"
    Info: State "|i2c|i2c_st:U4|i2c_state.data" uses code string "000010000000001"
    Info: State "|i2c|i2c_st:U4|i2c_state.start1" uses code string "000100000000001"
    Info: State "|i2c|i2c_st:U4|i2c_state.start2" uses code string "001000000000001"
    Info: State "|i2c|i2c_st:U4|i2c_state.stop1" uses code string "010000000000001"
    Info: State "|i2c|i2c_st:U4|i2c_state.dis_clk1" uses code string "100000000000001"
Info: Registers with preset signals will power-up high
Info: 4 registers lost all their fanouts during netlist optimizations. The first 4 are displayed below.
    Info: Register "i2c_st:U4|i2c_state~88" lost all its fanouts during netlist optimizations.
    Info: Register "i2c_st:U4|i2c_state~89" lost all its fanouts during netlist optimizations.
    Info: Register "i2c_st:U4|i2c_state~90" lost all its fanouts during netlist optimizations.
    Info: Register "i2c_st:U4|i2c_state~91" lost all its fanouts during netlist optimizations.
Info: Implemented 115 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 3 output pins
    Info: Implemented 9 bidirectional pins
    Info: Implemented 96 logic cells
Info: Generated suppressed messages file E:/Study FPGA/I2C/i2c.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Allocated 142 megabytes of memory during processing
    Info: Processing ended: Fri Apr 04 20:19:31 2008
    Info: Elapsed time: 00:00:04


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/Study FPGA/I2C/i2c.map.smsg.