i2c.tan.rpt

I2C总线的逻辑代码.Verilog编写!很好用.调试成功.

; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; reg_clk_in      ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+------------------------------+------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                         ; To                           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------+------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 245.10 MHz ( period = 4.080 ns )                    ; i2c_st:U4|bit_cntr[2]        ; i2c_st:U4|i2c_rdata[5]       ; clock      ; clock    ; None                        ; None                      ; 3.819 ns                ;
; N/A                                     ; 251.70 MHz ( period = 3.973 ns )                    ; i2c_st:U4|i2c_state.data     ; i2c_st:U4|i2c_rdata[6]       ; clock      ; clock    ; None                        ; None                      ; 3.712 ns                ;
; N/A                                     ; 251.76 MHz ( period = 3.972 ns )                    ; i2c_st:U4|scl                ; i2c_st:U4|i2c_rdata[6]       ; clock      ; clock    ; None                        ; None                      ; 3.711 ns                ;
; N/A                                     ; 253.74 MHz ( period = 3.941 ns )                    ; i2c_st:U4|bit_cntr[0]        ; i2c_st:U4|sda                ; clock      ; clock    ; None                        ; None                      ; 3.680 ns                ;
; N/A                                     ; 255.36 MHz ( period = 3.916 ns )                    ; i2c_st:U4|scl                ; i2c_st:U4|i2c_rdata[4]       ; clock      ; clock    ; None                        ; None                      ; 3.655 ns                ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                    ; i2c_st:U4|scl                ; i2c_st:U4|i2c_rdata[5]       ; clock      ; clock    ; None                        ; None                      ; 3.651 ns                ;
; N/A                                     ; 258.60 MHz ( period = 3.867 ns )                    ; i2c_st:U4|i2c_state.data     ; i2c_st:U4|i2c_rdata[5]       ; clock      ; clock    ; None                        ; None                      ; 3.606 ns                ;
; N/A                                     ; 265.46 MHz ( period = 3.767 ns )                    ; i2c_st:U4|bit_cntr[1]        ; i2c_st:U4|sda                ; clock      ; clock    ; None                        ; None                      ; 3.506 ns                ;
; N/A                                     ; 266.38 MHz ( period = 3.754 ns )                    ; i2c_st:U4|scl                ; i2c_st:U4|bit_cntr[1]        ; clock      ; clock    ; None                        ; None                      ; 3.493 ns                ;
; N/A                                     ; 266.38 MHz ( period = 3.754 ns )                    ; i2c_st:U4|scl                ; i2c_st:U4|bit_cntr[0]        ; clock      ; clock    ; None                        ; None                      ; 3.493 ns                ;
; N/A                                     ; 271.00 MHz ( period = 3.690 ns )                    ; i2c_st:U4|i2c_state.data     ; i2c_st:U4|i2c_rdata[4]       ; clock      ; clock    ; None                        ; None                      ; 3.429 ns                ;
; N/A                                     ; 273.75 MHz ( period = 3.653 ns )                    ; i2c_st:U4|i2c_state.w_add    ; i2c_st:U4|sda                ; clock      ; clock    ; None                        ; None                      ; 3.392 ns                ;
; N/A                                     ; 274.73 MHz ( period = 3.640 ns )                    ; i2c_st:U4|i2c_state.data     ; i2c_st:U4|i2c_rdata[7]       ; clock      ; clock    ; None                        ; None                      ; 3.379 ns                ;
; N/A                                     ; 274.88 MHz ( period = 3.638 ns )                    ; i2c_clk:U3|scl_tick          ; i2c_st:U4|i2c_state.idle     ; clock      ; clock    ; None                        ; None                      ; 3.377 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_st:U4|scl                ; i2c_st:U4|i2c_rdata[3]       ; clock      ; clock    ; None                        ; None                      ; 3.369 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_st:U4|scl                ; i2c_st:U4|i2c_rdata[2]       ; clock      ; clock    ; None                        ; None                      ; 3.368 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_st:U4|scl                ; i2c_st:U4|i2c_rdata[1]       ; clock      ; clock    ; None                        ; None                      ; 3.365 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_clk:U3|scl_tick          ; i2c_st:U4|i2c_state.data     ; clock      ; clock    ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_clk:U3|scl_tick          ; i2c_st:U4|bit_cntr[1]        ; clock      ; clock    ; None                        ; None                      ; 3.326 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_clk:U3|scl_tick          ; i2c_st:U4|bit_cntr[0]        ; clock      ; clock    ; None                        ; None                      ; 3.326 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_st:U4|bit_cntr[0]        ; i2c_st:U4|i2c_rdata[0]       ; clock      ; clock    ; None                        ; None                      ; 3.325 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_st:U4|i2c_state.start1   ; i2c_st:U4|sda                ; clock      ; clock    ; None                        ; None                      ; 3.319 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_wreg:U1|i2c_go           ; i2c_st:U4|i2c_rdata[6]       ; clock      ; clock    ; None                        ; None                      ; 3.279 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_st:U4|i2c_state.dev_add2 ; i2c_st:U4|sda                ; clock      ; clock    ; None                        ; None                      ; 3.266 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_st:U4|scl                ; i2c_st:U4|i2c_rdata[7]       ; clock      ; clock    ; None                        ; None                      ; 3.185 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_st:U4|bit_cntr[0]        ; i2c_st:U4|i2c_rdata[6]       ; clock      ; clock    ; None                        ; None                      ; 3.165 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_st:U4|bit_cntr[1]        ; i2c_st:U4|i2c_rdata[6]       ; clock      ; clock    ; None                        ; None                      ; 3.164 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_st:U4|scl                ; i2c_st:U4|i2c_state.idle     ; clock      ; clock    ; None                        ; None                      ; 3.146 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_clk:U3|cntr[0]           ; i2c_clk:U3|scl_tick          ; clock      ; clock    ; None                        ; None                      ; 3.145 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_st:U4|scl                ; i2c_st:U4|scl_en             ; clock      ; clock    ; None                        ; None                      ; 3.143 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_st:U4|i2c_state.data     ; i2c_st:U4|i2c_rdata[3]       ; clock      ; clock    ; None                        ; None                      ; 3.142 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_st:U4|i2c_state.data     ; i2c_st:U4|i2c_rdata[2]       ; clock      ; clock    ; None                        ; None                      ; 3.141 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; i2c_st:U4|i2c_state.data     ; i2c_st:U4|i2c_rdata[1]       ; clock      ; clock    ; None                        ; None                      ; 3.138 ns                ;