gal_16v8.v

基于GAL16V8D的一个时钟整开逻辑代码.Verilog编写!

module	gal_16v8(
		sclk,
		in_clk,
		
		out_clk,
		clk_en
		);
		
input	sclk;
input	in_clk;

output	out_clk;
output	clk_en;

wire	sclk;
wire	in_clk;

wire	out_clk;
reg	clk_en;

reg	[2:0]	sclk_counter;

//aiways @(posedge sclk or negedge in_clk)
always @(posedge sclk)
	if (in_clk==0)
		sclk_counter<=0;
	else if(sclk_counter[2]!=1)
		sclk_counter<=sclk_counter+1;
		
always @*
	if (sclk_counter<4)
		clk_en<=1;
	else
		clk_en<=0;
		
assign	out_clk = clk_en & in_clk;

endmodule