countertest.vhd

vhdl实现的计数器

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:10:23 08/11/2007 
-- Design Name: 
-- Module Name:    countertest - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity countertest is
port(
    clk,reset:in std_logic;
	 clkout:out std_logic
	 );
end countertest;

architecture Behavioral of countertest is
signal cout:std_logic_vector(3 downto 0);
signal clktemp:std_logic :='0';
begin
process(clk,reset)
begin
    if(reset='1')then
	     cout<="0000";
		 -- clkout<='0';
	 elsif(clk'event and clk= '1')then
        if(cout="0100")then
            cout<="0000";
            clktemp<=not clktemp;
        else
            cout<=cout+1;
            clktemp<=clktemp;
        end if;
        clkout<=clktemp;
     end if;
end process;	  

end Behavioral;