choadd.vhd

VHDL的数字钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity choadd is
port(cho,add:in std_logic;
     addh,addm,ena:out std_logic);
end choadd;
architecture one of choadd is
signal s:integer range 0 to 3;
 begin
  process(cho,add,s)
   begin
    if s<4 then
     if rising_edge(cho) then s<=s+1;
     end if;
    else s<=0;
    end if;
     case s is
      when 0=>addh<='0';addm<='0';ena<='0';
      when 1=>addh<=add;addm<='0';ena<='0';
      when 2=>addm<=add;addh<='0';ena<='0';
      when 3=>addh<='0';addm<='0';ena<='1';
      when others=>null;
     end case;
end process;
end one;