soundclock.vhd

VHDL的数字钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity soundclock is
  port(clk1khz,ena,tfm,tfh,clk1hz: in std_logic;
       sound:out std_logic);     
  end soundclock;
architecture one of soundclock is
signal a:std_logic;
begin
 process(clk1khz, clk1hz, tfm, tfh, ena, a)
  begin
   if ena='1' then
    if tfm='1' and tfh='1' then a<=clk1khz;
    else a<='0';
    end if;
   else a<='0';
   end if;
 sound<=clk1hz and a;
 end process;
end one;