choicedate.vhd

VHDL的数字钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity choicedate is
port(cho:in std_logic;
     enn,eny,enr:out std_logic);
end ;
architecture one of choicedate is
signal s:integer range 0 to 3;
 begin
  process(cho)
   begin
    if rising_edge(cho) then
     case s is
      when 0=>s<=1;enn<='1';eny<='0';enr<='0';
      when 1=>s<=2;eny<='1';enn<='0';enr<='0';
      when 2=>s<=3;enr<='1';enn<='0';eny<='0';
      when 3=>s<=0;enn<='0';enr<='0';eny<='0';
      when others=>null;
     end case;
    end if;
end process;
end one;