ri.vhd

来自「VHDL的数字钟」· VHDL 代码 · 共 44 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ri is
port (clk, clk1khz, ena, yf: in std_logic;
                mf: in std_logic_vector(1 downto 0);
              cout: out std_logic;
            dr, qr: out std_logic_vector(3 downto 0));
end ri;
architecture one of ri is
 signal dri, qri, nd, nq: std_logic_vector (3 DOWNTO 0);
begin
 process (clk,clk1khz,ena,dri,qri,nd,nq,yf,mf)
   begin
   if ena='0' then
     dri<="0001";
     qri<="0000";
     nq<="0011";
     nd<="0001";
   elsif rising_edge(clk1khz) then
      case yf is
       when '1' =>       
        if mf="00" then nd<="1001"; nq<="0010";
        end if;
       when '0' =>
        if mf="00" then nd<="1000"; nq<="0010";
        end if;
       when others=>
        null;
      end case;
      if mf="10" then nd<="0001"; nq<="0011";
      elsif mf="01" then nd<="0000"; nq<="0011";
      end if;
   end if;
   if ena='1' and rising_edge(clk) then
      if (qri=nq and dri=nd) then qri<="0000"; dri<="0001"; cout<='1';
      elsif dri<"1001" then dri<=dri+1;  cout<='0';
      elsif dri="1001" then qri<=qri+1; dri<="0000"; cout<='0';
      end if;
   end if;
  dr<=dri;
  qr<=qri;
 end process;
end one;