fir1.map.summary

基于verilog的FIR滤波器

Analysis & Synthesis Status : Successful - Tue Jun 05 18:08:20 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Web Edition
Revision Name : FIR1
Top-level Entity Name : FIR1
Family : Cyclone
Total logic elements : 101
Total pins : 16
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0