second.txt

一个简单的用vhdl写的计秒功能的小程序.

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    23:29:42 01/08/2005 
-- Design Name: 
-- Module Name:    second - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity second is
    Port ( clk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           en : in  STD_LOGIC;
			  admin : out  STD_LOGIC;
			  secout_l: out std_logic_vector(3 downto 0);
           secout_h: out std_logic_vector(2 downto 0));
end second; 

architecture Behavioral of second is

begin    
process (clk,en,clr)
   variable count_l:std_logic_vector(3 downto 0);
	variable count_h:std_logic_vector(2 downto 0);
    begin
	 if (en='1' and clr='1') then
	    count_l:="0000";
	    count_h:="000";
		 admin<='0';
	 elsif(clk'event and clk='1' and en='1')then
	       secout_l<=count_l;
	       secout_h<=count_h;
	      if(count_l="1001")then
			   count_l:="0000";
			   count_h:=count_h+'1';  
			     if(count_h="110")then
				     admin<='1';
			        count_h:="000";	 
				  else
				     admin<='0';
				  end if;
			else	
           count_l:=count_l+'1';	  
			end if;
	 end if;
	 end process;		
end Behavioral;