gateen.v

根据外部控制指令和送入的波形参数

         if(clksum2 ==16'h4)    
           clksum2   <=16'h0;
         else
           clksum2   <=clksum2  +16'h1;

always @(posedge CLK_33M or negedge RESET)
  if(!RESET)
     CLK_MOD=1'b0;
  else
    if(clksum2==16'h4)
       CLK_MOD=~CLK_MOD;
		 
always @(posedge CLK_33M or negedge RESET)
  if(!RESET)
     CLK_DA1=1'b1;
  else
    if(clksum2==16'h4)
       CLK_DA1=~CLK_DA1;		 


/*
always@(posedge CLK_33M or negedge RESET)
   if(!RESET)
     begin
       CLK_MOD <=1'b0;
     end
   else
      if(clksum2 ==16'h2)    //6 DIVIDE FREQUENCE；
        begin
           CLK_MOD <=~CLK_MOD;
         end
*/

/*           
always@(posedge CLK_50M or negedge RESET)
   if(!RESET)
       CLK_FPGA<=1'b1;
   else
       CLK_FPGA<= ~ CLK_FPGA;
*/

/*
always@(posedge CLK_50M or negedge RESET)
    if(!RESET)
       CLK_FPGA <=1'b1;
    else
       if(clksum1 ==16'h1)
         CLK_FPGA <=~ CLK_FPGA;
*/                  
/*
always@(posedge CLK_24M or negedge RESET)
   if(!RESET)
     begin
       CLK_MOD <=1'b0;
     end
   else
      if(clksum2 ==16'h2)    //6 DIVIDE FREQUENCE；
        begin
           CLK_MOD <=~CLK_MOD;
         end
*/
/**************test 5M shixian *********/



/*
always@(posedge CLK_24M or negedge RESET)
   if(!RESET)
     begin
        CLK_DA1 <=1'b0;
     end
   else
      if(clksum2 ==16'h2)    //6 DIVIDE FREQUENCE；
        begin
             CLK_DA1 <=~CLK_DA1;
        end
*/

always@(posedge CLK_33M or negedge RESET)    
   if(!RESET)
      sel_ad_out <=1'b1;
   else
      if(core_busy_negedge ==1'b1)
          sel_ad_out <=~sel_ad_out;
         
always@(posedge CLK_33M or negedge RESET)    
   if(!RESET)
      DPC_SEL_PQ <=1'b1;
   else
      if(FRAME_SYN_posedge ==1'b1)
          DPC_SEL_PQ <=~DPC_SEL_PQ;

always@(posedge CLK_33M or negedge RESET)
   if(!RESET)
      cs_ad <=1'b1;				 //0 gaiwei 1
   else
      cs_ad <=1'b0;
      
always@(posedge CLK_33M or negedge RESET)
   if(!RESET)
        begin
          busy_cnt<=4'h0;
        end
   else
      if(FRAME_SYN_posedge==1'b1)
          begin 
            busy_cnt<=4'h0;
          end
      else
         if(core_busy_negedge ==1'b1)  
             busy_cnt <=busy_cnt+1'h1;
             
 
always@(posedge CLK_33M or negedge RESET)
    if(!RESET)
       DPC_RAM_SEL <=1'b1;        //起始放在前64K处；
    else
       if((DPC_ADDR_SWITCH ==1'b1)||(FRAME_SYN_posedge==1))     //从 8个就切换；
          DPC_RAM_SEL <=~DPC_RAM_SEL;         //调试时候要注意这里的初始极性要搞对；
                                              //20ms翻一次；
/*
always@(posedge CLK_50M or negedge RESET)
    if(!RESET)                               //测试单通道时用P1片选对
      begin
        DPC_OUT_CS_P1 <=1'b1;  //0有效；
        DPC_OUT_CS_P2 <=1'b1;
        DPC_OUT_CS_Q1 <=1'b1;
        DPC_OUT_CS_Q2 <=1'b1;
      end
    else
      begin
        DPC_OUT_CS_P1 <=1'b0;
        DPC_OUT_CS_P2 <=1'b1;
        DPC_OUT_CS_Q1 <=1'b1;
        DPC_OUT_CS_Q2 <=1'b1;
      end
*/
//这里所
always@(posedge CLK_33M or negedge RESET)
    if(!RESET)
      begin
        DPC_OUT_CS_P1 <=1'b1;  //0有效；
        DPC_OUT_CS_P2 <=1'b1;
        DPC_OUT_CS_Q1 <=1'b1;
        DPC_OUT_CS_Q2 <=1'b1;
      end
    else
       if(DPC_SEL_PQ ==1'b1)
          if(DPC_RAM_SEL ==1'b1)   //前64K；
            begin
               DPC_OUT_CS_P1 <=1'b0;
               DPC_OUT_CS_P2 <=1'b1;
               DPC_OUT_CS_Q1 <=1'b1;
               DPC_OUT_CS_Q2 <=1'b1;
            end
          else                    //后16K
            begin
               DPC_OUT_CS_P1 <=1'b1; 
               DPC_OUT_CS_P2 <=1'b0;
               DPC_OUT_CS_Q1 <=1'b1;
               DPC_OUT_CS_Q2 <=1'b1;
            end          
       else
          if(DPC_RAM_SEL ==1'b1)
            begin
               DPC_OUT_CS_Q1 <=1'b0;
               DPC_OUT_CS_Q2 <=1'b1;
	       DPC_OUT_CS_P1 <=1'b1; 
               DPC_OUT_CS_P2 <=1'b1;
            end
          else
            begin
               DPC_OUT_CS_Q1 <=1'b1;
               DPC_OUT_CS_Q2 <=1'b0;
	       DPC_OUT_CS_P1 <=1'b1; 
               DPC_OUT_CS_P2 <=1'b1;
            end   

/*
always@(posedge CLK_33M or negedge RESET)
    if(!RESET)
      begin
        DSP_IN_CS_P1 <=1'b1;  //0有效； ADSP_MS[1]  
        DSP_IN_CS_P2 <=1'b1;
        DSP_IN_CS_Q1 <=1'b1;
        DSP_IN_CS_Q2 <=1'b1;
      end
    else
	    if(DPC_SEL_PQ ==1'b1)
		  begin      
		     if(DSP_CS_1 ==1'b1)
			     begin
	   		      DSP_IN_CS_Q1 <=1'b0;
   			      DSP_IN_CS_P1 <=1'b1;
				  DSP_IN_CS_Q2 <=1'b1;
   			      DSP_IN_CS_P2 <=1'b1;
		         end
 			 if(DSP_CS_2 ==1'b1)
			     begin
	   		      DSP_IN_CS_Q1 <=1'b1;
				  DSP_IN_CS_P1 <=1'b1;
   			      DSP_IN_CS_Q2 <=1'b0;
   			      DSP_IN_CS_P2 <=1'b1; 
				end
		 end
       else
		  begin   
	         if(DSP_CS_1 ==1'b1)
			   begin
	   		      DSP_IN_CS_P1 <=1'b0;
   			      DSP_IN_CS_P2 <=1'b1;
				  DSP_IN_CS_Q1 <=1'b1;
   			      DSP_IN_CS_Q2 <=1'b1;
		       end
 			 if(DSP_CS_2 ==1'b1)
			   begin
	   		      DSP_IN_CS_P1 <=1'b1;
   			      DSP_IN_CS_P2 <=1'b0;
				  DSP_IN_CS_Q1 <=1'b1;
   			      DSP_IN_CS_Q2 <=1'b1;	   
			   end
         end
*/
//这里三态的写法保证读写和片选的时序对应；
assign DSP_IN_CS_Q1 =(DPC_SEL_PQ ==1'b1)?ADSP_MS[1]:1'b1;
assign DSP_IN_CS_Q2 =(DPC_SEL_PQ ==1'b1)?ADSP_MS[2]:1'b1;
assign DSP_IN_CS_P1 =(DPC_SEL_PQ ==1'b0)?ADSP_MS[1]:1'b1;
assign DSP_IN_CS_P2 =(DPC_SEL_PQ ==1'b0)?ADSP_MS[2]:1'b1;

/*
always@(posedge CLK_33M or negedge RESET)
    if(!RESET)
      begin
        DSP_IN_CS_P1 <=1'b1;  //0有效； ADSP_MS[1]  
        DSP_IN_CS_P2 <=1'b1;
        DSP_IN_CS_Q1 <=1'b1;
        DSP_IN_CS_Q2 <=1'b1;
      end
    else
	    if(DPC_SEL_PQ ==1'b1)
//	    if(DPC_SEL_PQ ==1'b0)
			     begin
	   		      DSP_IN_CS_Q1 <=ADSP_MS[1];
				  DSP_IN_CS_Q2 <=ADSP_MS[2];
				  DSP_IN_CS_P1 <=1'b1;  //0有效； ADSP_MS[1]  
                  DSP_IN_CS_P2 <=1'b1;
		         end
        else
			   begin
	   		      DSP_IN_CS_P1 <=ADSP_MS[1];
   			      DSP_IN_CS_P2 <=ADSP_MS[2];
                  DSP_IN_CS_Q1 <=1'b1;  //0有效 ADSP_MS[1]  
                  DSP_IN_CS_Q2 <=1'b1;
		       end
*/

/*
always@(posedge CLK_33M or negedge RESET)
    if(!RESET)
      begin
        DSP_IN_CS_P1 <=1'b1;  //0有效； ADSP_MS[1]  
        DSP_IN_CS_P2 <=1'b1;
        DSP_IN_CS_Q1 <=1'b1;
        DSP_IN_CS_Q2 <=1'b1;
      end
    else
	  begin
        DSP_IN_CS_P1 <=ADSP_MS[2];
		DSP_IN_CS_P2 <=1'b1;
        DSP_IN_CS_Q1 <=1'b1;
        DSP_IN_CS_Q2 <=1'b1;
//   	    DSP_IN_CS_P2 <=ADSP_MS[2];
	  end
*/
 endmodule