data_path.v

根据外部控制指令和送入的波形参数

module data_path(
                 CLK_FPGA,
                 RESET,
                 core_enable,
                 ref,
                 ref_mem_mode,
//                 work_mode,
                 PRF_IN,
                 ID_in,
                 QD_in,
//                 ref_mem_data,
                 ref_size,
                 PRF_SEL,
                 exp_out,
//                 ID_out,
//                 QD_out,
                 cmp_id,
                 cmp_qd,
                 core_busy,
                 core_d_valid,
                 core_ready,
				 test,
//				 dout,
                 in_index,
                 out_index,
					  size_we
                );

input             CLK_FPGA;
input             RESET;
input             core_enable;
input             ref;
input             ref_mem_mode;
//input             work_mode;
input             PRF_IN;
input [15:0]      ID_in;
input [15:0]      QD_in;
input [3:0]       ref_size;
input             PRF_SEL;
output [5:0]      exp_out;
output [15:0]     cmp_id;
output [15:0]     cmp_qd;
//output [15:0]     ID_out;
//output [15:0]     QD_out;
output            core_busy;
output            core_d_valid;
output            core_ready;
output [12:0]     in_index;
output [12:0]     out_index;       
//output [31:0]     dout;
output [7:0]      test;
output            size_we;
wire  [31:0]      ref_mem_data;
wire  [31:0]      ref_mem_data_4k;
wire  [31:0]      ref_mem_data_8k;

wire  [15:0]      cmp_id;
wire  [15:0]      cmp_qd;
wire  [13:0]      ref_mem_addr;
reg   [12:0]      R1_addr;
reg   [12:0]      R2_addr;
wire  [12:0]      in_index;
wire  [12:0]     out_index; 
wire              start;
wire              core_enable;
wire              PRF_SEL;
wire              core_busy;
wire              core_ready;
wire              RAM_EN_8k;
wire              RAM_EN_4k;
wire              ref_mem_mode;
reg              ref_mem_we;
wire              REF_EXP_WE;
wire [1:0]        test_mode;
//wire[15:0]        ID_in_test;
//wire[15:0]        QD_in_test;
wire              size_we;
//wire[31:0]        dout;

wire 					CLK_FPGA;
wire              RESET;
reg               test_ram_we;
reg [12:0]        test_addr;
wire  [3:0]            ref_size;
wire              ref;
wire [15:0]      ID_in;
wire [15:0]      QD_in;
wire [5:0]      exp_out;
wire [7:0]      test;
wire            DLL_CLK;
wire [31:0]     din;
//assign test[1:0] =ref_mem_data_8k[1:0];
//wire				 work_mode;
//assign ID_out=(work_mode==1'b1)?cmp_id:ID_in_test;     //直通测试、脉压路径的选择；

//assign ID_out =cmp_id;

//assign ID_out =ID_in_test;
//assign QD_out=(work_mode==1'b1)?cmp_qd:QD_in_test;

//assign QD_out=cmp_qd;

//assign QD_out =QD_in_test;
//assign ref_mem_addr=(PRF_SEL==1'b0)?R2_addr_8k:R2_addr_4k;
assign ref_mem_addr[12:0]=R2_addr;
assign ref_mem_addr[13]=1'b0;//REF_EXP_WE;
assign RAM_EN_8k   =(PRF_SEL==1'b0)?1'b1:1'b0;
assign RAM_EN_4k   =(PRF_SEL==1'b1)?1'b1:1'b0;
//assign ref_mem_data =(PRF_SEL==1'b1)? ref_mem_data_4k:ref_mem_data_8k;
assign ref_mem_data =(PRF_SEL==1'b0)? ref_mem_data_8k:ref_mem_data_4k;

reg [7:0]        delay;
reg              PRF_IN_delay1;
reg              PRF_IN_delay2;
reg              PRF_IN_delay;
wire             PRF_IN_posedge;

assign PRF_IN_posedge =(~PRF_IN_delay1)&&(PRF_IN);
//assign size_we =(core_enable==1)&&(( PRF_IN) &&(!PRF_IN_delay2));     //占2拍；
assign size_we =(core_enable==1)&&((delay[0] ) &&(!delay[2])); 
//assign REF_EXP_WE =1'b0;//(core_enable==1)&&(delay[2]&&(!delay[4]));
assign start =(core_enable==1)&&(delay[5]&&(!delay[7]));

always@(posedge CLK_FPGA or negedge RESET)
   if(!RESET)
      PRF_IN_delay1<=1'b0;
   else
      PRF_IN_delay1<=PRF_IN;

always@(posedge CLK_FPGA or negedge RESET)
   if(!RESET)
      PRF_IN_delay2<=1'b0;
   else
      PRF_IN_delay2<=PRF_IN_delay1;
      
always@(posedge CLK_FPGA or negedge RESET)
    if(!RESET)
      begin
        delay<=8'h0;
      end
    else
       delay<={delay[6:0],PRF_IN};


always@(posedge CLK_FPGA or negedge RESET)
  if(!RESET)
    ref_mem_we <=1'b0;
  else
//    if((core_enable)&&(core_ready)&&(ref_mem_mode))
    if(core_ready==1'b1)
      ref_mem_we <=1'b1;
    else
      ref_mem_we <=1'b0;


//assign ref_mem_we =(core_ready==1'b1)?CLK_FPGA:1'b0;  //kan kan shi fou yao mai chong da ;
assign test_mode   ={core_ready,core_d_valid};
assign din         ={ID_in,QD_in};
//assign {ID_out,QD_out}   =dout ;        //32位数据格式I占高位，Q占低位；

/*
always@(posedge CLK_FPGA or negedge RESET)      //这里可能和核的时序上配合存在问题；
   if(!RESET)
      begin
        test_addr<=13'h0;
        test_ram_we<=1'b1;       //1:写有效需确认；
      end
   else
      begin
         case(test_mode)
            2'b10:      begin
                          test_addr<=in_index;
                          test_ram_we<=1'b1;
                        end
            2'b01:      begin
                          test_addr<=out_index;
                          test_ram_we<=1'b0;
                        end
            default:    begin
                          test_addr<=in_index;
                          test_ram_we<=1'b1;
                        end
         endcase
      end
*/
always@(posedge CLK_FPGA or negedge RESET)
   if(!RESET)
       R1_addr <=13'h0;
   else
       if(core_ready==1'b1)
         R1_addr <=in_index;        //这里缓两拍；根据实
	   else
	     R1_addr <=13'h0;


always@(posedge CLK_FPGA or negedge RESET)
   if(!RESET)
       R2_addr <=13'h0;
   else
       R2_addr <=R1_addr;
/*
assign test[0]=in_index[0];
assign test[1]=ref_mem_we;
assign test[2]=start;
assign test[3]=ID_in[0];
assign test[4]=out_index[0];
assign test[5]=ref_mem_addr[12];
assign test[6]=cmp_qd[2];
assign test[7]=cmp_id[2];
*/
assign test=cmp_id[7:0];
assign ref_mem_data_fan={ref_mem_data[15:0],ref_mem_data[31:16]};
p4954_440  P4954_440 (                                                                                                       
                      .I_IN(ID_in),//ID_in),      //       
                      .Q_IN(QD_in),//QD_in),          
                      .CE  (core_enable),            
                      .CLK (CLK_FPGA),      
                      .RST (!RESET) ,         //wai mian lai de fuwei shi di dianpin; 
                      .START(start),               
                      .REF_MEM_DATA(ref_mem_data),    
//                      .REF_MEM_DATA(32'h00007fff),            
                      .REF_MEM_ADDR(ref_mem_addr),         
                      .REF_MEM_WE(ref_mem_we),       
//                      .REF_MEM_MODE(ref_mem_mode),   
                      .REF_MEM_MODE(1'b1),             
                      .REF (ref),    //   1'b0 
                      .SIZE(ref_size)  ,  
//                      .SIZE(4'b1101)  ,                  
                      .SIZE_WE (size_we), 
                      .IN_INDEX(in_index),  
                      .OUT_INDEX(out_index), 
                      .RFD (core_ready)  ,     
                      .BUSY(core_busy) ,        
                      .DVAL_OUT(core_d_valid),              
                      .I_OUT(cmp_id),           
                      .Q_OUT(cmp_qd),         
                      .EXP_OUT(exp_out), //(exp_out) ,              
		                .DCM_RST(1'b0) ,
		                .LOCK(),
                      .DLL_CLK(DLL_CLK)							 
                      );       
/*							                  
STR_SEQ   str_seq(
                  .CORE_ENABLE(core_enable),                                        
                  .CLK_FPGA(CLK_FPGA),                                           
                   .PRF_IN(PRF_IN),                                               
                  .RST(RESET),                                                
                  .REF_EXP_WE(REF_EXP_WE),                     
                  .SIZE_WE (size_we),                         
                  .START(start)                               
                  );

*/

/*
ref_bsr_8k ref_bsr_8k(                     //参RAM例化，初始化文件没LOAD；
        	      .addr(R1_addr),       //对RAMCORE参考地址一拍；
        	      .clk(CLK_FPGA),
        	      .dout(ref_mem_data_8k),
        	      .en(RAM_EN_8k)
        	      );
*/

/*
ref_bsr_4k ref_bsr_4k(                     //参RAM例化，初始化文LOAD
        	      .A(R1_addr),       //对RAM的读地址要提前写CORE参
        	      .CLK(CLK_FPGA),
        	      .QSPO_CE(RAM_EN_4k),
        	      .QSPO(ref_mem_data_4k)
        	      );

*/
/*
bypass_ram  bypass_ram(
                       .addr(test_addr),
                       .clk(CLK_FPGA),
                       .din(din),
                       .dout(dout),
                       .en(!work_mode),
                       .sinit(RESET),             //ram reset;
                       .we(test_ram_we)
                       );
*/
/*
testram testram (
	.addra(in_index),
	.addrb(out_index),
	.clka(CLK_FPGA),
	.clkb(CLK_FPGA),
	.dina(din),
	.doutb(dout),
	.wea(core_ready));
*/
/*
testram testram (
	.addra(R1_addr),
	.addrb(out_index),
	.clka(CLK_FPGA),
	.clkb(CLK_FPGA),
	.dina(din),
	.doutb(dout),
	.wea(core_ready));
*/
endmodule