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根据外部控制指令和送入的波形参数

/***this section applicate mainly for the correct of dsp read**************/ 
/*
assign FB_TEST[1] =DSP_IN_CS_P1;
assign FB_TEST[2] =ADSP_RDH;//DSP_IN_CS_P2;
assign FB_TEST[3] =DSP_IN_CS_Q1;
assign FB_TEST[4] =ADSP_WRH;//DSP_IN_CS_Q2;
assign FB_TEST[5] =DPC_SEL_PQ;
assign FB_TEST[6] =ADSP_MS[1];
assign FB_TEST[7] =ADSP_MS[2];
*/

//assign FB_TEST[8:6] =test_sig[7:5];//DPC_OUT_ADDR[15:13];

//assign FB_TEST[4:1] =DPC_OUT_ADDR[3:0];

/*
assign FB_TEST[3:1] =test_sig[7:5];
assign FB_TEST[4] =test_sig[4];// is DPC_RAM_SEL
assign FB_TEST[7:5] =test_sig[2:0];
*/

//assign FB_TEST =router_test;
assign FB_TEST[6:1] =exp_out;
//assign FB_TEST[8:1] =router_test[7:0];



//assign FB_TEST[2:1] =QD_in[1:0];
//assign FB_TEST[4:1] =ID_out[3:0];
//assign FB_TEST[5] =  PRF_SEL;
//assign FB_TEST[7:6] =coeff;
//assign FB_TEST =coeff;
//assign FB_TEST[1] =CLK_MOD;

//assign FB_TEST[8:1] =DPC_OUT_DATA[7:0];
//assign FB_TEST[7]   =ID_out[1];
//assign FB_TEST[7]   =QD_in ;   
//assign FB_TEST[6]   =read_ad;
//assign FB_TEST[5:2] =in_index[3:0];
//assign FB_TEST[1] =AD_IN_ADDR[0];

//always@(negedge CLK_33M_OUT or negedge RESET)


always@(negedge CLK_40M or negedge RESET)
   if(!RESET)
      DPC_OUT_DATA <=32'b0;
   else
     begin
       DPC_OUT_DATA <={DATA_ID_out,DATA_QD_out}; ;
     end
reg [15:0] ID_out_tmp;
reg [15:0] QD_out_tmp;

//assign ID_tmp =(ID_out[15] ==1'b0)?ID_out:(~ID_out+1'b1);
//assign QD_tmp =(QD_out[15] ==1'b0)?QD_out:(~QD_out+1'b1);
always @(negedge CLK_40M or negedge RESET)
    if(!RESET)
		  ID_out_tmp <=16'h0;
	 else
        ID_out_tmp <=ID_out;

always @(negedge CLK_40M or negedge RESET)
    if(!RESET)
		  QD_out_tmp <=16'h0;
	 else
        QD_out_tmp <=QD_out;

always @(negedge CLK_40M or negedge RESET)
    if(!RESET)
		  ID_tmp <=16'h0;
	 else
	   if(ID_out[15] ==1'b0)
		   ID_tmp <=ID_out;
		else
         ID_tmp	<=(~ID_out_tmp+1'b1);

always @(negedge CLK_40M or negedge RESET)
    if(!RESET)
		  QD_tmp <=16'h0;
	 else
	   if(QD_out[15] ==1'b0)
		   QD_tmp <=QD_out;
		else
         QD_tmp	<=(~QD_out_tmp+1'b1);

  
//assign DATA_ID_tmp =(ID_tmp/4'hb)*(exp_out+1'b1);
//assign DATA_QD_tmp =(QD_tmp/4'hb)*(exp_out+1'b1);
always @(negedge CLK_40M or negedge RESET)
    if(!RESET)
		  DATA_ID_tmp123 <=16'h0;
	 else
	     DATA_ID_tmp123 <=ID_tmp/12;
		  
always @(negedge CLK_40M or negedge RESET)
    if(!RESET)
		  DATA_QD_tmp123 <=16'h0;
	 else
	     DATA_QD_tmp123 <=QD_tmp/12;
		  
/*****************************/

always @(negedge CLK_40M or negedge RESET)
    if(!RESET)
		  exp_out <=16'h0;
	 else
	     exp_out <=exp_out123;		  

always @(negedge CLK_40M or negedge RESET)
    if(!RESET)
		  DATA_ID_tmp <=16'h0;
	 else
	     DATA_ID_tmp <=DATA_ID_tmp123*(exp_out+1'b1);
		  
always @(negedge CLK_40M or negedge RESET)
    if(!RESET)
		  DATA_QD_tmp <=16'h0;
	 else
	     DATA_QD_tmp <=DATA_QD_tmp123*(exp_out+1'b1);

/*****************************/		  
		  



//assign DATA_ID_tmp =(ID_tmp);  //test;
//assign DATA_QD_tmp =(QD_tmp);

always @(negedge CLK_40M or negedge RESET)
    if(!RESET)
		  DATA_ID_out <=16'h0;
	 else
	   if(ID_out[15] ==1'b0)
		   DATA_ID_out <=DATA_ID_tmp;
		else
         DATA_ID_out	<=(~DATA_ID_tmp+1'b1);
			
always @(negedge CLK_40M or negedge RESET)
    if(!RESET)
		  DATA_QD_out <=16'h0;
	 else
	   if(QD_out[15] ==1'b0)
		   DATA_QD_out <=DATA_QD_tmp;
		else
         DATA_QD_out	<=(~DATA_QD_tmp+1'b1);

		
//P&R SYNTHESIS  time constraint is over		
//assign DATA_ID_out =(ID_out[15] ==1'b0)?DATA_ID_tmp:(~DATA_ID_tmp+1'b1);
//assign DATA_QD_out =(QD_out[15] ==1'b0)?DATA_QD_tmp:(~DATA_QD_tmp+1'b1);

//assign  DPC_OUT_DATA ={DATA_ID_out,DATA_QD_out}; 

interface    interface(
                 .CLK_50M(CLK_40M), 
                 .RESET(RESET),
                 .PRF_500_976_in(PRF_500_976_in),
                 .FKL_Hprf_in(FKL_Hprf_in),
                 .YT_NT_in(YT_NT_in),
                 .F2F_DATA_in(F2F_DATA_in),
                 .PRF_500_976(PRF_500_976),
                 .FKL_Hprf(FKL_Hprf),
                 .YT_NT(YT_NT),
                 .F2F_DATA(F2F_DATA)
                      );



ctrl_reg  ctrl_reg(
                 .CLK(),            //dsp clk;33M 暂时未用；
                 .CLK_FPGA(CLK_40M),
                 .RESET(RESET),          
                 .ref_mem_mode(ref_mem_mode),
//               .ref_mem_we(),
                 .ref_size(ref_size),
	              .ref(ref),
                 .FKL_Hprf(FKL_Hprf),  //no use;
                 .PRF_500_976(PRF_500_976),
                 .YT_NT(YT_NT),     //test mode use instead  PRF_500_976 面板上测试用的；
                 .PRF_SEL(PRF_SEL),
                 .work_mode(work_mode),
                 .frame_prf_num(frame_prf_num)       
                        );

data_path      data_path(
                 .CLK_FPGA(CLK_40M),
                 .RESET(RESET),
                 .core_enable(core_enable),
                 .ref(ref),
                 .ref_mem_mode(ref_mem_mode),
//                 .work_mode(work_mode),
                 .PRF_IN(PRF_IN_TMP),
                 .ID_in(ID_in),
                 .QD_in(QD_in),
                 .ref_size(ref_size),
//                 .PRF_SEL(PRF_SEL),
                 .PRF_SEL(PRF_SEL),
                 .exp_out(exp_out123),
				 .cmp_id(ID_out),
				 .cmp_qd(QD_out),
//                 .ID_out(ID_out),
//                 .QD_out(QD_out),
//                 .core_start(core_start),
                 .core_busy(core_busy),
                 .core_d_valid(core_d_valid),
                 .core_ready(core_ready),
//				 .dout(DPC_OUT_DATA_tmp),
                 .test(coeff),
                 .in_index(in_index),
                 .out_index(out_index),
                 .size_we(size_we)					  
                        );


gate_en        gate_en(
 //                .CLK_50M(CLK_40M),
                 .CLK_24M(CLK_24M),
					  .CLK_33M(CLK_40M),
                 .CLK_MOD(CLK_MOD),
                 .CLK_DA1(CLKDA1),
//                 .CLK_FPGA(CLK_50M),
                 .FRAME_SYN(FRAME_SYN_TMP),
                 .RESET(RESET),
//                 .prf_in(PRF_IN),        
                 .PRF_SEL(PRF_SEL),
                 .work_mode(work_mode),
                 .core_enable(core_enable),
                 .core_busy(core_busy),      //因为乒乓操作是按PRF来做的，一个PRF做乒，下一个做乓，
                 .core_ready(core_ready),     //rfd;
                 .core_d_valid(core_d_valid),
 //                .frame_prf_num(frame_prf_num),   //?没被使用？
                 .out_index(out_index),
                 .sel_ad_out(AD_IN_SEL),        //PRF翻转CORE_BUSY
                 .read_ad(read_ad),
                 .cs_ad(AD_IN_CS),
                 .read_ad_en(read_ad_en),
                 .DPC_OUT_CS_P1(DPC_OUT_CS_P1),    //按帧同步操作，积累到8-10个PRF转换输出乒RAM区-64K；
                 .DPC_OUT_CS_P2(DPC_OUT_CS_P2),                                                //-16K；
                 .DPC_OUT_CS_Q1(DPC_OUT_CS_Q1),    //按帧同步操作，积累到8-10个PRF转换输出乓RAM区-64K；
                 .DPC_OUT_CS_Q2(DPC_OUT_CS_Q2),           
					  .DSP_IN_CS_P1(DSP_IN_CS_P1),
					  .DSP_IN_CS_P2(DSP_IN_CS_P2),
					  .DSP_IN_CS_Q1(DSP_IN_CS_Q1),
					  .DSP_IN_CS_Q2(DSP_IN_CS_Q2),                                     //-16K
                 .DPC_WEP(DPC_WEP),          //DPC写乒RAM；
                 .DPC_WEQ(DPC_WEQ),          //DPC写乓RAM；
                 .DPC_OUT_ADDR(DPC_OUT_ADDR),
                 .REF_RAM4K_SEL(REF_RAM4K_SEL),        //这里的参考RAM使能不起作用了；
                 .REF_RAM8K_SEL(REF_RAM8K_SEL),
					  .DPC_SEL_PQ(DPC_SEL_PQ),
					  .ADSP_MS(ADSP_MS),
					  .test(test_sig)      
                       );

/*
testram testram (
	.addra(in_index),
	.addrb(out_index),
	.clka(CLK_33M_OUT),
	.clkb(CLK_33M_OUT),
	.dina(din),
	.doutb(DPC_OUT_DATA_tmp),
	.wea(core_ready));

*/
                   
router_mod     router_mod (
                 .CLK_FPGA(CLK_40M),
                 .CLK_MOD_in(CLK_MOD),
                 .RESET(RESET),
                 .core_d_valid(core_d_valid),
                 .out_index(out_index),
                 .QD_in(QD_out),
                 .ID_in(ID_out),
//                 .QD_in(),
//                 .ID_in(),
                 .MOD_DATA(MOD_DATA),
					  .QD_tmp(),
					  .ID_tmp(),
					  .size_we(size_we),       //yongyu router_mod dpram data 0utput;
                 .test(router_test)					  
                        );
	 
endmodule