top.v

根据外部控制指令和送入的波形参数

// altitude measure radar pulse compress process;
//author:baosr;
//version:1.0;
//data:2006.08.28
//module partition description;
//module hierarchy:
//top------interface
//---------core_ctrl_reg
//---------data_path
//---------mod_compute
//---------gate_en

//是否要+时钟和复位BUF驱动？

module top(
//----------GLOBLE SIGNAL----------
            CLK_40M,
            CLK_50M_IN,
            CLK_24M,
            CLK_MOD,
            CLKDA1,
            RESET_in,                //0:valid;
            PRF_IN,
            FRAME_SYN,            //if frame_syn out?
            PRF_500_976_in,
            FKL_Hprf_in,
            YT_NT_in,
//-----------AD SAMPLE---------------
            AD_IN_ADDR,
            AD_IN_SEL,
            AD_IN_DATA,
            AD_RD,
            AD_IN_CS,
            AD_RD_EN,
//-----------dpc_out-----------------            
            DPC_OUT_ADDR,
            DPC_OUT_CS_P1,
            DPC_OUT_CS_P2,
            DPC_OUT_CS_Q1,
            DPC_OUT_CS_Q2,
            DPC_OUT_DATA,
            DPC_WEP,
            DPC_WEQ,
//-----------DSP READ-----------------            
            DSP_IN_CS_P1,
            DSP_IN_CS_P2,
            DSP_IN_CS_Q1,
            DSP_IN_CS_Q2,
            DSP_IN_PEN,
            DSP_IN_QEN,
            DSP_RDP,
            DSP_RDQ,
            MOD_DATA,
//-----------BACKUP SECTION------------
            ADSP_MS,
            ADSP_RDH,
            ADSP_WRH,
            ADSP_ADDR,
            ADSP_DATA,
            ADSP_IRQ,
            A_FLG,
            FPGAB_FLG,
            F2F_DATA_in,
				F2F_DATA_out,
            F_NC,
            FB_TEST
            );

output         CLKDA1;
input         CLK_40M;
input         CLK_50M_IN;
input         CLK_24M;
output        CLK_MOD;
input         RESET_in;
input         PRF_IN;
input         FRAME_SYN;
input         PRF_500_976_in;
input         FKL_Hprf_in;
input         YT_NT_in;

output [14:0] AD_IN_ADDR;
output        AD_IN_SEL;
input  [15:0] AD_IN_DATA;
output        AD_RD ;
output        AD_IN_CS ;
output        AD_RD_EN ;

output  [15:0]DPC_OUT_ADDR ;
output        DPC_OUT_CS_P1;
output        DPC_OUT_CS_P2;
output        DPC_OUT_CS_Q1;
output        DPC_OUT_CS_Q2;
output  [31:0]  DPC_OUT_DATA;
output        DPC_WEP;
output        DPC_WEQ;
output        DSP_IN_CS_P1;			 
output        DSP_IN_CS_P2;
output        DSP_IN_CS_Q1;
output        DSP_IN_CS_Q2;
output        DSP_IN_PEN;		
output        DSP_IN_QEN;			
output        DSP_RDP;				
output        DSP_RDQ;			
output  [15:0]MOD_DATA;

input   [2:0] ADSP_MS ; 
input         ADSP_RDH ;    
input         ADSP_WRH ;
input   [5:0] ADSP_ADDR;
input   [7:0] ADSP_DATA;
output  [2:0] ADSP_IRQ;						
input   [3:0] A_FLG;							 
output  [3:1] FPGAB_FLG;  

input   [13:0]F2F_DATA_in;
output  [1:0] F2F_DATA_out;
output  [16:9]F_NC ;
output  [8:1] FB_TEST;

wire    RESET;
wire    PRF_500_976;
wire    FKL_Hprf;
wire    YT_NT;
wire    [13:0]    F2F_DATA;
wire    [1:0]     F2F_DATA_out;
wire    [12:0]    in_index;
wire    [12:0]    out_index;
//wire              CLK_FPGA;
wire              CLK_MOD;
wire              core_d_valid;
wire              core_ready;
wire              core_busy;
wire              core_enable;
wire              work_mode;
wire              PRF_SEL;
wire    [4:0]     frame_prf_num;
wire    [3:0]     ref_size;
wire              ref;
wire    [14:0]    AD_IN_ADDR;

wire    [15:0]    ID_in_tmp;
wire    [15:0]    QD_in_tmp;

reg     [15:0]    ID_in;
reg     [15:0]    QD_in;
wire    [15:0]    ID_out;
wire    [15:0]    QD_out;
wire              PRF_IN_TMP;
wire              FRAME_SYN_TMP;
wire    [7:0]     test_sig;
wire    [2:0]     ADSP_IRQ;
wire              DPC_SEL_PQ;
wire              DSP_IN_PEN;
wire              DSP_IN_QEN;
wire              DSP_RDP;
wire              DSP_RDQ;
//wire              CLK_33M_OUT;
wire              CLK_50M;
//wire              CLK_50M_IN;
wire              CLK_40M;
wire              RESET_in;
wire              read_ad;
wire              read_ad_en;

reg [31:0]       DPC_OUT_DATA;
//reg [31:0]        DPC_OUT_DATA;
wire [31:0]       din;
wire [7:0]        coeff;
wire [7:0]        router_test;
reg [5:0]        exp_out;
wire [5:0]        exp_out123;
reg [15:0] QD_tmp;
reg [15:0] ID_tmp;

reg [15:0]   DATA_ID_tmp;
reg [15:0]   DATA_QD_tmp;
reg [15:0]   DATA_ID_out;
reg [15:0]   DATA_QD_out;

reg [15:0]   DATA_ID_tmp123;
reg [15:0]   DATA_QD_tmp123;
//wire              clk20m;
//reg  [1:0]        clksum;           

/*
IBUFG x_1(
               .I(CLK_50M_IN),
					.O(CLK_50M)
					);
*/

/*
IBUFG x_3(
               .I(CLK_33M),
					.O(CLK_33M_OUT)
					);
*/
IBUFG x_2(
               .I(RESET_in),
					.O(RESET)
					);


//assign  DPC_OUT_DATA={ID_out,QD_out};  //输出为I+Q，32位，和设计要求?
/*
always @(posedge CLK_40M_OUT or negedge RESET)
    if(!RESET)
      clksum  <=  0;
    else
      clksum  <=  clksum  + 1;

//assign clk6m  =  ~clksum[2];
assign clk20m =  clksum[0];
*/



assign  AD_RD = read_ad;
assign  AD_RD_EN = 1'b0;//~read_ad_en;
assign  AD_IN_ADDR={1'b0,in_index,(~CLK_40M ) && (read_ad)};
//assign  ID_in_tmp=(CLK_33M_OUT==1'b1)?AD_IN_DATA:16'hzzzz;
//assign  QD_in_tmp=(CLK_33M_OUT==1'b0)?AD_IN_DATA:16'hzzzz;
assign  PRF_IN_TMP =(work_mode==1'b0)?PRF_IN:F2F_DATA_in[1];
assign  FRAME_SYN_TMP =(work_mode==1'b0)?FRAME_SYN:F2F_DATA_in[2];

//assign  DPC_OUT_DATA_tmp ={ID_out,QD_out};  //输出为I+Q32?

always@(CLK_40M or AD_IN_DATA)   //attention compare tri with latch;  tri is incorrect,but latch is correct; 
   if(CLK_40M==1'b0)
     begin   
       ID_in <=AD_IN_DATA;
     end
   else
     begin 
       QD_in <=AD_IN_DATA;
	 end

//assign din  ={ID_in,QD_in};

/*
always @(posedge CLK_33M_OUT)
   ID_in <= AD_IN_DATA;

always @(negedge CLK_33M_OUT)
   QD_in <= AD_IN_DATA;
*/
assign 	ADSP_IRQ[1] = PRF_IN_TMP;
assign   ADSP_IRQ[2] = FRAME_SYN_TMP;

assign  DSP_IN_PEN =ADSP_RDH;     
assign  DSP_IN_QEN = ADSP_RDH;   //ADSP_WRH;
assign  DSP_RDP	 =	ADSP_WRH;  //ADSP_RDH;
assign  DSP_RDQ    = ADSP_WRH;

assign  F2F_DATA_out[0] =AD_IN_SEL;
assign  F2F_DATA_out[1] =DPC_SEL_PQ;

/*test IO specify   */

assign F_NC[16] = DPC_SEL_PQ;//DPC_SEL_PQ;  //CLK_33M_OUT;//
assign F_NC[10] = core_busy;//test_sig[1];//DPC_RAM_SEL;//core_busy;//CLK_50M_IN;
assign F_NC[11] = CLK_40M;//PRF_IN_TMP;//ADSP_MS[2];//core_d_valid;//RESET;//
assign F_NC[12] = core_ready;//test_sig[3];//ADSP_MS[1];//core_ready;//
assign F_NC[13] = CLK_MOD;  //test_sig[4];//CLK_33M_OUT;// DPC_OUT_CS_P1;//F2F_DATA_in[1];//DPC_OUT_CS_P1;//
assign F_NC[14] = core_d_valid;     //DPC_OUT_CS_P2;//F2F_DATA_in[2];//DPC_OUT_CS_P2;//
assign F_NC[15] = DPC_WEP;//~(~read_ad_en);//DPC_WEP;//DPC_OUT_CS_Q1;//DPC_OUT_CS_Q1;//
assign F_NC[9]  = DPC_WEQ;//AD_IN_CS; //DPC_WEQ;//DPC_OUT_CS_Q2;//DPC_OUT_CS_Q2;//

/*
assign F_NC[16]   =CLK_MOD;
assign F_NC[15]   =CLK_33M_OUT;
assign F_NC[14]   =RESET;
assign F_NC[13]   =AD_IN_SEL;
//assign F_NC[12]   =test_sig[0];
assign F_NC[11]   =test_sig[1];
assign F_NC[10]   =test_sig[2];
assign F_NC[9]   = ref;
*/
/*
assign F_NC[16:14] =DPC_OUT_ADDR[15:13];
assign F_NC[13]   =AD_IN_SEL;
assign F_NC[12]   =test_sig[0];  //FRAME_SYN_posedge;
assign F_NC[11]   =test_sig[2];  //DPC_ADDR_SWITCH;
assign F_NC[10]   =test_sig[3];  //DSP_CS_1;
assign F_NC[9]    =test_sig[4];  //DSP_CS_2;
*/
//assign FB_TEST =ID_in[7:0];//test  1012;