interface.v

根据外部控制指令和送入的波形参数

//the major function of interface module is syn with clock and eliminate sub_stabilization;

module interface(
                 CLK_50M, 
                 RESET,
                 PRF_500_976_in,
                 FKL_Hprf_in,
                 YT_NT_in,
                 F2F_DATA_in,
                 PRF_500_976,
                 FKL_Hprf,
                 YT_NT,
                 F2F_DATA
                 );

input         CLK_50M;                 
input         RESET;               
input         PRF_500_976_in;         
input         FKL_Hprf_in;         
input         YT_NT_in;         
input[13:0]   F2F_DATA_in;   
output        PRF_500_976 ;        
output        FKL_Hprf;         
output        YT_NT;         
output[13:0]  F2F_DATA;
//reg           RESET_delay;
reg           PRF_500_976;                 
reg           FKL_Hprf;                 
reg           YT_NT;                 
reg [13:0]    F2F_DATA;

/*
always@(posedge CLK_50M)     //2次消除sub_stabilization；
    begin  
      RESET_delay<=RESET_in;
      RESET<=RESET_delay;
    end
*/
      
always@(posedge CLK_50M or negedge RESET)
    if(!RESET)
       begin
          PRF_500_976<=1'bz;
          FKL_Hprf<=1'bz;
          YT_NT<=1'bz;
          F2F_DATA<=14'hzzz;
       end
    else
       begin
          PRF_500_976<=1'b0;//PRF_500_976_in;
          FKL_Hprf<=1'b1;//FKL_Hprf_in;
          YT_NT<=1'b0;//YT_NT_in;
          F2F_DATA<=F2F_DATA_in; 
       end
             
endmodule