p4954_440.v

根据外部控制指令和送入的波形参数

module p4954_440(
     I_IN,        
     Q_IN,        
     CE,          
     CLK,         
     RST,         
     START,       
     REF_MEM_DATA,
     REF_MEM_ADDR,
     REF_MEM_WE,  
     REF_MEM_MODE,
     REF,         
     SIZE,        
     SIZE_WE,     
     IN_INDEX,    
     OUT_INDEX,   
     RFD,
     BUSY,        
     DVAL_OUT,    
     I_OUT,       
     Q_OUT,       
     EXP_OUT,     
     DCM_RST,     
     LOCK,
     DLL_CLK	  
               );


input [15:0] I_IN;
input [15:0] Q_IN;
input CE;
input CLK;
input RST;
input START;
input [31:0] REF_MEM_DATA;
input [13:0] REF_MEM_ADDR;
input REF_MEM_WE;  
input REF_MEM_MODE;
input REF;         
input [3:0] SIZE;        
input SIZE_WE;     
output [12:0] IN_INDEX;    
output [12:0] OUT_INDEX;   
output RFD;
output BUSY;        
output DVAL_OUT;    
output [15:0] I_OUT;       
output [15:0] Q_OUT;       
output [5:0] EXP_OUT;     
input DCM_RST;     
output LOCK;          
output DLL_CLK;
    
wire CLK0_W;
wire DLL_CLK;
wire GND;

assign GND = 1'b0;
//=============================================================================
// Sample Clock DCM
//=============================================================================
    //BUFG Instantiation
    BUFG  S_BUFG (  
                  .I(CLK0_W),  
                  .O(DLL_CLK)
                 );
	 
    // Attributes for functional simulation//
    // synopsys translate_off
       defparam S_DCM.DLL_FREQUENCY_MODE = "LOW";
       defparam S_DCM.DUTY_CYCLE_CORRECTION = "TRUE";
       defparam S_DCM.STARTUP_WAIT = "FALSE";
    // synopsys translate_on

    // Instantiate the DCM primitive//
	 DCM S_DCM ( 
               .CLKFB(DLL_CLK), 
               .CLKIN(CLK), 
               .DSSEN(GND), 
               .PSCLK(GND), 
		         .PSEN(GND), 
               .PSINCDEC(GND), 
               .RST(DCM_RST), 
               .CLK0(CLK0_W),  
		         .LOCKED(LOCK)
              );

// attribute declarations for synthesis
     /* synopsys attribute
     DLL_FREQUENCY_MODE "LOW" 
     DUTY_CYCLE_CORRECTION "TRUE" 
	  STARTUP_WAIT "FALSE" 
     */

     //synthesis attribute DLL_FREQUENCY_MODE of S_DCM is "LOW" 
	  //synthesis attribute DUTY_CYCLE_CORRECTION of S_DCM is "TRUE" 
	  //synthesis attribute STARTUP_WAIT of S_DCM is "FALSE" 


 
//attribute box_type of pls_cmpr_4k16a is	"black_box"

pls_cmpr_8k16a pls_cmpr1(
     .I_IN(I_IN),        
     .Q_IN(Q_IN),        
     .CE(CE),          
     .CLK(DLL_CLK),         
     .RST(RST),         
     .START(START),       
     .REF_MEM_DATA(REF_MEM_DATA),
     .REF_MEM_ADDR(REF_MEM_ADDR),
     .REF_MEM_WE(REF_MEM_WE),  
     .REF_MEM_MODE(REF_MEM_MODE),
     .REF(REF),         
     .SIZE(SIZE),        
     .SIZE_WE(SIZE_WE),     
     .IN_INDEX(IN_INDEX),    
     .OUT_INDEX(OUT_INDEX),   
     .RFD(RFD),
     .BUSY(BUSY),        
     .DVAL_OUT(DVAL_OUT),    
     .I_OUT(I_OUT),       
     .Q_OUT(Q_OUT),       
     .EXP_OUT(EXP_OUT)     
    );


endmodule

module pls_cmpr_8k16a(
     I_IN,        
     Q_IN,        
     CE,          
     CLK,         
     RST,         
     START,       
     REF_MEM_DATA,
     REF_MEM_ADDR,
     REF_MEM_WE,  
     REF_MEM_MODE,
     REF,         
     SIZE,        
     SIZE_WE,     
     IN_INDEX,    
     OUT_INDEX,   
     RFD,
     BUSY,        
     DVAL_OUT,    
     I_OUT,       
     Q_OUT,       
     EXP_OUT     
               
               )/* synthesis	 syn_black_box	*/;

input [15:0] I_IN;
input [15:0] Q_IN;
input CE;
input CLK;
input RST;
input START;
input [31:0] REF_MEM_DATA;
input [13:0] REF_MEM_ADDR;
input REF_MEM_WE;  
input REF_MEM_MODE;
input REF;         
input [3:0] SIZE;        
input SIZE_WE;     
output [12:0] IN_INDEX;    
output [12:0] OUT_INDEX;   
output RFD;
output BUSY;        
output DVAL_OUT;    
output [15:0] I_OUT;       
output [15:0] Q_OUT;       
output [5:0] EXP_OUT;     

endmodule