pisa.def

来自「一个很有名的硬件模拟器。可以模拟CPU」· DEF 代码 · 共 2,259 行 · 第 1/5 页

/* This doesn't look like -*- C -*-, but it is! */

/* pisa.def - SimpleScalar portable ISA (pisa) machine definition */

/* SimpleScalar(TM) Tool Suite
 * Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
 * All Rights Reserved. 
 * 
 * THIS IS A LEGAL DOCUMENT, BY USING SIMPLESCALAR,
 * YOU ARE AGREEING TO THESE TERMS AND CONDITIONS.
 * 
 * No portion of this work may be used by any commercial entity, or for any
 * commercial purpose, without the prior, written permission of SimpleScalar,
 * LLC ([e-mail]). Nonprofit and noncommercial use is permitted
 * as described below.
 * 
 * 1. SimpleScalar is provided AS IS, with no warranty of any kind, express
 * or implied. The user of the program accepts full responsibility for the
 * application of the program and the use of any results.
 * 
 * 2. Nonprofit and noncommercial use is encouraged. SimpleScalar may be
 * downloaded, compiled, executed, copied, and modified solely for nonprofit,
 * educational, noncommercial research, and noncommercial scholarship
 * purposes provided that this notice in its entirety accompanies all copies.
 * Copies of the modified software can be delivered to persons who use it
 * solely for nonprofit, educational, noncommercial research, and
 * noncommercial scholarship purposes provided that this notice in its
 * entirety accompanies all copies.
 * 
 * 3. ALL COMMERCIAL USE, AND ALL USE BY FOR PROFIT ENTITIES, IS EXPRESSLY
 * PROHIBITED WITHOUT A LICENSE FROM SIMPLESCALAR, LLC ([e-mail]).
 * 
 * 4. No nonprofit user may place any restrictions on the use of this software,
 * including as modified by the user, by any other authorized user.
 * 
 * 5. Noncommercial and nonprofit users may distribute copies of SimpleScalar
 * in compiled or executable form as set forth in Section 2, provided that
 * either: (A) it is accompanied by the corresponding machine-readable source
 * code, or (B) it is accompanied by a written offer, with no time limit, to
 * give anyone a machine-readable copy of the corresponding source code in
 * return for reimbursement of the cost of distribution. This written offer
 * must permit verbatim duplication by anyone, or (C) it is distributed by
 * someone who received only the executable form, and is accompanied by a
 * copy of the written offer of source code.
 * 
 * 6. SimpleScalar was developed by Todd M. Austin, Ph.D. The tool suite is
 * currently maintained by SimpleScalar LLC ([e-mail]). US Mail:
 * 2395 Timbercrest Court, Ann Arbor, MI 48105.
 * 
 * Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
 */


/* This file defines all aspects of the SimpleScalar instruction set
 * architecture.  Each instruction set in the architecture has a DEFINST()
 * macro call included below.  The contents of a instruction definition are
 * as follows:
 *
 *   DEFINST(<enum>,			<opcode>,
 *	     <opname>,			<operands>,
 *	     <fu_req>,			<iflags>,
 *	     <output deps...>,		<input deps...>,
 *	     <expr>)
 *
 * Where:
 *
 *   <enum>	- is an enumerator that is returned when an instruction is
 *		  decoded by SS_OP_ENUM()
 *   <opcode>	- is the opcode of this instruction
 *   <opname>   - name of this instruction as a string, used by disassembler
 *   <operands>	- specified the instruction operand fields and their printed
 * 		  order for disassembly, used by disassembler, the recognized
 *		  operand field are (the instruction format is detailed in
 *		  the header file ss.h):
 *		    J - target field
 *		    j - PC relative target (offset + PC)
 *		    s - S register field
 *		    b - S register field (base register)
 *		    t - T register field
 *		    d - D register field
 *		    S - S register field (FP register)
 *		    T - T register field (FP register)
 *		    D - D register field (FP register)
 *		    o - load address offset (offset)
 *		    i - signed immediate field value
 *		    u - unsigned immediate field value
 *		    U - upper immediate field value
 *		    H - shift amount immediate field value
 *		    B - break code
 *
 *   <fu_req>	- functional unit requirements for this instruction
 *   <iflags>	- instruction flags, accessible via the SS_OP_FLAGS()
 *		  macro, flags are defined with F_* prefix in ss.h
 *   <output deps...>
 *		- a list of up to two output dependency designators, the
 *		  following designators are recognized (place an DNA in any
 *		  unused fields:
 *		    DGPR(N)   - general purpose register N
 *		    DGPR_D(N) - double word general purpose register N
 *		    DCGPR(N)  - general purpose register conditional on
 *			        pre/post- increment/decrement mode
 *		    DFPR_L(N) - floating-point register N, as word
 *		    DFPR_F(N) - floating-point reg N, as single-prec float
 *		    DFPR_D(N) - floating-point reg N, as double-prec double
 *		    DHI	      - HI result register
 *		    DLO	      - LO result register
 *		    DFCC      - floating point condition codes
 *		    DCPC      - current PC
 *		    DNPC      - next PC
 *		    DNA	      - no dependence
 *
 *   <input deps...>
 *		- a list of up to three input dependency designators, the
 *		  designators are defined above (place an DNA in any unused
 *		  fields.
 *
 *   <expr>	- a C expression that implements the instruction being
 * 		  defined, the expression must modify all architected state
 *		  affected by the instruction's execution, by default, the
 *		  next PC (NPC) value defaults to the current PC (CPC) plus
 *		  SS_INST_SIZE, as a result, only taken branches need to set
 *		  NPC
 *
 *		  The following predefined macros are available for use in
 *		  DEFINST() instruction expressions to access the value of
 *		  instruction operand/opcode field values:
 *
 *		    RS	    - RS register field value
 *		    RT	    - RT register field value
 *		    RD	    - RD register field value
 *		    FS	    - RS register field value
 *		    FT	    - RT register field value
 *		    FD	    - RD register field value
 *		    BS	    - RS register field value
 *		    TARG    - jump target field value
 *		    OFS	    - signed offset field value
 *		    IMM	    - signed offset field value
 *		    UIMM    - unsigned offset field value
 *		    SHAMT   - shift amount field value
 *		    BCODE   - break code field value
 *
 *		  To facilitate the construction of performance simulators
 *		  (which may want to specialize their architected state
 *		  storage format), all architected register and memory state
 *		  is accessed through the following macros:
 *
 *		    GPR(N)         - read general purpose register N
 *		    SET_GPR(N,E)   - write general purpose register N with E
 *		    GPR_D(N)       - read double word general purpose reg N
 *		    SET_GPR_D(N,E) - write double word gen purpose reg N w/ E
 *		    FPR_L(N)       - read floating-point register N, as word
 *		    SET_FPR_L(N,E) - floating-point reg N, as word, with E
 *		    FPR_F(N)       - read FP reg N, as single-prec float
 *		    SET_FPR_F(N,E) - write FP reg N, as single-prec float w/ E
 *		    FPR_D(N)       - read FP reg N, as double-prec double
 *		    SET_FPR_D(N,E) - write FP reg N, as double-prec double w/E
 *		    HI	           - read HI result register
 *		    SET_HI(E)      - write HI result register with E
 *		    LO	           - read LO result register
 *		    SET_LO(E)      - write LO result register with E
 *		    FCC	           - read floating point condition codes
 *		    SET_FCC(E)     - write floating point condition codes w/ E
 *		    CPC	           - read current PC register
 *		    NPC	           - read next PC register
 *		    SET_NPC(E)     - write next PC register with E
 *		    TPC	           - read target PC register
 *		    SET_TPC(E)     - write target PC register with E
 *
 *		    READ_SIGNED_BYTE(A)   - read signed byte from address A
 *		    READ_UNSIGNED_BYTE(A) - read unsigned byte from address A
 *		    READ_SIGNED_HALF(A)   - read signed half from address A
 *		    READ_UNSIGNED_HALF(A) - read unsigned half from address A
 *		    READ_WORD(A)          - read word from address A
 *		    WRITE_BYTE(E,A)       - write byte value E to address A
 *		    WRITE_HALF(E,A)       - write half value E to address A
 *		    WRITE_WORD(E,A)       - write word value E to address A
 *
 *		  Finally, the following helper functions are available to
 *		  assist in the construction of instruction expressions:
 *
 *		    INC_DEC(E,N,S) - execute E and update N as per pre/post-
 *				     incr/decr addressing sementics for an
 *				     access of S bytes
 *		    OVER(X,Y)      - check for overflow for X+Y, both signed
 *		    UNDER(X,Y)	   - check for umderflow for X-Y, both signed
 *		    DIV0(N)	   - check for divide by zero, N is denom
 *		    INTALIGN(N)    - check double word int reg N alignment
 *		    FPALIGN(N)	   - check double word FP reg N alignment
 *		    TALIGN(T)	   - check jump target T alignment
 */

/* no operation */
#define NOP_IMPL							\
  {									\
    /* nada... */							\
  }
DEFINST(NOP,		0x00,
	"nop",		"",
	IntALU,		F_ICOMP,
	DNA, DNA,	DNA, DNA, DNA)

/*
 * control operations
 */

#define JUMP_IMPL							\
  {									\
    SET_TPC((CPC & 036000000000) | (TARG << 2));			\
    SET_NPC((CPC & 036000000000) | (TARG << 2));			\
  }
DEFINST(JUMP,			0x01,
	"j",			"J",
	NA, 			F_CTRL|F_UNCOND|F_DIRJMP,
	DNA, DNA, 		DNA, DNA, DNA)

#define JAL_IMPL							\
  {									\
    SET_TPC((CPC & 036000000000) | (TARG << 2));			\
    SET_NPC((CPC & 036000000000) | (TARG << 2));			\
    SET_GPR(31, CPC + 8);						\
  }
DEFINST(JAL,			0x02,
	"jal",			"J",
	IntALU,			F_CTRL|F_UNCOND|F_DIRJMP|F_CALL,
	DGPR(31), DNA,	 	DNA, DNA, DNA)

#define JR_IMPL								\
  {									\
    if (GPR(RS) & 0x7)							\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_TPC(GPR(RS));							\
    SET_NPC(GPR(RS));							\
  }
DEFINST(JR, 			0x03,
	"jr", 			"s", 
	NA, 			F_CTRL|F_UNCOND|F_INDIRJMP,
	DNA, DNA,		DGPR(RS), DNA, DNA)

#define JALR_IMPL							\
  {									\
    if (GPR(RS) & 0x7)							\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_GPR(RD, CPC + 8);						\
    SET_TPC(GPR(RS));							\
    SET_NPC(GPR(RS));							\
  }
DEFINST(JALR,	 		0x04,
	"jalr", 		"d,s",
	IntALU,			F_CTRL|F_UNCOND|F_INDIRJMP|F_CALL,
	DGPR(RD), DNA,		DGPR(RS), DNA, DNA)

#define BEQ_IMPL							\
  {									\
    SET_TPC(CPC + 8 + (OFS << 2));					\
    if (GPR(RS) == GPR(RT))						\
      SET_NPC(CPC + 8 + (OFS << 2));					\
  }
DEFINST(BEQ,			0x05,
	"beq",			"s,t,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RS), DGPR(RT), DNA)

#define BNE_IMPL							\
  {									\
    SET_TPC(CPC + 8 + (OFS << 2));					\
    if (GPR(RS) != GPR(RT))						\
      SET_NPC(CPC + 8 + (OFS << 2));					\
  }
DEFINST(BNE,			0x06,
	"bne",			"s,t,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RS), DGPR(RT), DNA)

#define BLEZ_IMPL							\
  {									\
    SET_TPC(CPC + 8 + (OFS << 2));					\
    if (GPR(RS) <= 0)							\
      SET_NPC(CPC + 8 + (OFS << 2));					\
  }
DEFINST(BLEZ,			0x07,
	"blez",			"s,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RS), DNA, DNA)

#define BGTZ_IMPL							\
  {									\
    SET_TPC(CPC + 8 + (OFS << 2));					\
    if (GPR(RS) > 0)							\
      SET_NPC(CPC + 8 + (OFS << 2));					\
  }
DEFINST(BGTZ,			0x08,
	"bgtz",			"s,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RS), DNA, DNA)

#define BLTZ_IMPL							\
  {									\
    SET_TPC(CPC + 8 + (OFS << 2));					\
    if (GPR(RS) < 0)							\
      SET_NPC(CPC + 8 + (OFS << 2));					\
  }
DEFINST(BLTZ,	 		0x09,
	"bltz", 		"s,j", 
	IntALU, 		F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RS), DNA, DNA)

#define BGEZ_IMPL							\
  {									\
    SET_TPC(CPC + 8 + (OFS << 2));					\
    if (GPR(RS) >= 0)							\
      SET_NPC(CPC + 8 + (OFS << 2));					\
  }
DEFINST(BGEZ, 			0x0a,
	"bgez", 		"s,j", 
	IntALU, 		F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RS), DNA, DNA)

#define BC1F_IMPL							\
  {									\
    SET_TPC(CPC + 8 + (OFS << 2));					\
    if (!FCC)								\
      SET_NPC(CPC + 8 + (OFS << 2));					\
  }
DEFINST(BC1F, 			0x0b,
	"bc1f", 		"j", 
	IntALU,			F_CTRL|F_COND|F_DIRJMP|F_FPCOND,
	DNA, DNA,		DFCC, DNA, DNA)

#define BC1T_IMPL							\
  {									\
    SET_TPC(CPC + 8 + (OFS << 2));					\
    if (FCC)								\
      SET_NPC(CPC + 8 + (OFS << 2));					\
  }
DEFINST(BC1T, 			0x0c,
	"bc1t", 		"j", 
	IntALU,			F_CTRL|F_COND|F_DIRJMP|F_FPCOND,
	DNA, DNA,		DFCC, DNA, DNA)


/*
 * load/store operations
 *
 * NOTE: the out-of-order issue simulator(s) require that load and store
 * address computation input dependencies be placed in slots 1 and 2 of
 * the input dependency list slot 0 is reserved for the input dependency
 * of store values for store instructions
 */

#define LB_IMPL								\
  {									\
    sbyte_t _result;							\
    enum md_fault_type _fault;						\
									\
    _result = READ_BYTE(GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    SET_GPR(RT, (word_t)(sword_t)_result);				\
  }
DEFINST(LB,			0x20,
	"lb",			"t,o(b)",
	RdPort,			F_MEM|F_LOAD|F_DISP,
	DGPR(RT), DNA,		DNA, DGPR(BS), DNA)

#define LBU_IMPL							\
  {									\
    byte_t _result;							\
    enum md_fault_type _fault;						\
									\
    _result = READ_BYTE(GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    SET_GPR(RT, (word_t)_result);					\
  }
DEFINST(LBU, 			0x22, 
	"lbu", 			"t,o(b)",
	RdPort, 		F_MEM|F_LOAD|F_DISP,
	DGPR(RT), DNA,		DNA, DGPR(BS), DNA)

#define LH_IMPL								\
  {									\
    shalf_t _result;							\
    enum md_fault_type _fault;						\
									\
    _result = READ_HALF(GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    SET_GPR(RT, (word_t)(sword_t)_result);				\
  }
DEFINST(LH, 			0x24,
	"lh",			"t,o(b)",
	RdPort,			F_MEM|F_LOAD|F_DISP,
	DGPR(RT), DNA,		DNA, DGPR(BS), DNA)

#define LHU_IMPL							\
  {									\
    half_t _result;							\
    enum md_fault_type _fault;						\
									\
    _result = READ_HALF(GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    SET_GPR(RT, (word_t)_result);					\
  }
DEFINST(LHU, 			0x26, 
	"lhu", 			"t,o(b)",
	RdPort, 		F_MEM|F_LOAD|F_DISP,
	DGPR(RT), DNA,		DNA, DGPR(BS), DNA)

#define LW_IMPL								\
  {									\
    word_t _result;							\
    enum md_fault_type _fault;						\
									\
    _result = READ_WORD(GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    SET_GPR(RT, _result);						\
  }
DEFINST(LW,			0x28,
	"lw", 			"t,o(b)",
	RdPort,			F_MEM|F_LOAD|F_DISP,
	DGPR(RT), DNA,		DNA, DGPR(BS), DNA)

#define DLW_IMPL							\
  {									\
    word_t _result_hi, _result_lo;					\
    enum md_fault_type _fault;						\
									\
    if ((RT) & 01)							\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    _result_hi = READ_WORD(GPR(BS) + OFS, _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    _result_lo = READ_WORD(GPR(BS) + OFS + 4, _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    SET_GPR(RT, _result_hi);						\
    SET_GPR((RT) + 1, _result_lo);					\
  }
DEFINST(DLW,			0x29,
	"dlw",			"t,o(b)",
	RdPort,			F_MEM|F_LOAD|F_DISP,
	DGPR_D(RT), DNA,	DNA, DGPR(BS), DNA)

#define L_S_IMPL							\
  {									\
    word_t _result;							\