pisa.def

来自「一个很有名的硬件模拟器。可以模拟CPU」· DEF 代码 · 共 2,259 行 · 第 1/5 页

    enum md_fault_type _fault;						\
									\
    _result = READ_WORD(GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    SET_FPR_L(FT, _result);						\
  }
DEFINST(L_S, 			0x2a,
	"l.s",			"T,o(b)",
	RdPort,			F_MEM|F_LOAD|F_DISP,
	DFPR_L(FT), DNA,	DNA, DGPR(BS), DNA)

#define L_D_IMPL							\
  {									\
    word_t _result_hi, _result_lo;					\
    enum md_fault_type _fault;						\
									\
    if ((FT) & 01)							\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    _result_hi = READ_WORD(GPR(BS) + OFS, _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    _result_lo = READ_WORD(GPR(BS) + OFS + 4, _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    SET_FPR_L(FT, _result_hi);						\
    SET_FPR_L((FT) + 1, _result_lo);					\
  }

DEFINST(L_D,			0x2b,
	"l.d",			"T,o(b)",
	RdPort,			F_MEM|F_LOAD|F_DISP,
	DFPR_D(FT), DNA,	DNA, DGPR(BS), DNA)

#if (!defined(MD_CROSS_ENDIAN) && defined(BYTES_BIG_ENDIAN)) || (defined(MD_CROSS_ENDIAN) && defined(BYTES_LITTLE_ENDIAN))
#define LWL_IMPL							\
  {									\
    md_addr_t _temp_bs;							\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    /* BS may == RT */							\
    _temp_bs = GPR(BS);							\
    _lr_temp = READ_WORD(WL_BASE(_temp_bs + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    SET_GPR(RT, ((GPR(RT) & WL_PROT_MASK1(_temp_bs + OFS))		\
		 | ((_lr_temp << (8 * WL_SIZE(_temp_bs + OFS)))		\
		    & ~WL_PROT_MASK1(_temp_bs + OFS))));		\
  }
DEFINST(LWL,			0x2c,
        "lwl",			"t,o(b)",
        RdPort,			F_MEM|F_LOAD|F_DISP,
        DGPR(RT), DNA,		DNA, DGPR(BS), DNA)

#define LWR_IMPL							\
  {									\
    md_addr_t _temp_bs;							\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    /* BS may == RT */							\
    _temp_bs = GPR(BS);							\
    _lr_temp = READ_WORD(WR_BASE(_temp_bs + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    SET_GPR(RT, ((GPR(RT) & ~WR_PROT_MASK1(_temp_bs + OFS))		\
		 | ((_lr_temp >> (8 * (4 - WR_SIZE(_temp_bs + OFS))))	\
		    & WR_PROT_MASK1(_temp_bs + OFS))));			\
  }
DEFINST(LWR,			0x2d,
        "lwr",			"t,o(b)",
        RdPort,			F_MEM|F_LOAD|F_DISP,
        DGPR(RT), DNA,		DNA, DGPR(BS), DNA)
#else /* defined BYTES_LITTLE_ENDIAN */
#define LWL_IMPL							\
  {									\
    md_addr_t _temp_bs;							\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    /* BS may == RT */							\
    _temp_bs = GPR(BS);							\
    _lr_temp = READ_WORD(WL_BASE(_temp_bs + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    SET_GPR(RT, ((GPR(RT) & WR_PROT_MASK1(_temp_bs + OFS))		\
		 | ((_lr_temp << (8 * (WL_SIZE(_temp_bs + OFS)-1)))	\
		    & ~WR_PROT_MASK1(_temp_bs + OFS))));		\
  }
DEFINST(LWL,			0x2c,
        "lwl",			"t,o(b)",
        RdPort,			F_MEM|F_LOAD|F_DISP,
        DGPR(RT), DNA,		DNA, DGPR(BS), DNA)

#define LWR_IMPL							\
  {									\
    md_addr_t _temp_bs;							\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    /* BS may == RT */							\
    _temp_bs = GPR(BS);							\
    _lr_temp = READ_WORD(WR_BASE(_temp_bs + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    SET_GPR(RT, ((GPR(RT) & ~WL_PROT_MASK2(_temp_bs + OFS))		\
		 | ((_lr_temp >> (8 * (WR_SIZE(_temp_bs + OFS)-1)))	\
		    & WL_PROT_MASK2(_temp_bs + OFS))));			\
  }
DEFINST(LWR,			0x2d,
        "lwr",			"t,o(b)",
        RdPort,			F_MEM|F_LOAD|F_DISP,
        DGPR(RT), DNA,		DNA, DGPR(BS), DNA)
#endif
  
#if 0
#define LWL_IMPL							\
  {									\
    md_addr_t _temp_bs;							\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    /* BS may == RT */							\
    _temp_bs = GPR(BS);							\
    _lr_temp = READ_WORD(WL_BASE(_temp_bs + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    SET_GPR(RT, ((GPR(RT) & WL_PROT_MASK(_temp_bs + OFS)) |		\
                      (_lr_temp & ~WL_PROT_MASK(_temp_bs + OFS))));	\
  }
DEFINST(LWL,			0x2c,
	"lwl",			"t,o(b)",
	RdPort,			F_MEM|F_LOAD|F_DISP,
	DGPR(RT), DNA,		DNA, DGPR(BS), DNA)
/* #else */
DEFINST(LWL,			0x2c,
	"lwl",			"t,o(b)",
	RdPort,			F_MEM|F_LOAD|F_DISP,
	DGPR(RT), DNA,		DNA, DGPR(BS), DNA,
	(ss_lr_temp = READ_WORD(WL_BASE(GPR(BS) + OFS)),
	 SET_GPR(RT, ((GPR(RT) & WL_PROT_MASK1(GPR(BS) + OFS)) |
		      ((ss_lr_temp << (8 * WL_SIZE(GPR(BS) + OFS))) 
		       & ~WL_PROT_MASK1(GPR(BS) + OFS))))))
#endif

#if 0
#define LWR_IMPL							\
  {									\
    md_addr_t _temp_bs;							\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    /* BS may == RT */							\
    _temp_bs = GPR(BS);							\
    _lr_temp = READ_WORD(WR_BASE(_temp_bs + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    SET_GPR(RT, ((GPR(RT) & WR_PROT_MASK(_temp_bs + OFS)) |		\
                      (_lr_temp & ~WR_PROT_MASK(_temp_bs + OFS))));	\
  }
DEFINST(LWR,			0x2d,
	"lwr",			"t,o(b)",
	RdPort,			F_MEM|F_LOAD|F_DISP,
	DGPR(RT), DNA,		DNA, DGPR(BS), DNA)
/* #else */
DEFINST(LWR,			0x2d,
	"lwr",			"t,o(b)",
	RdPort,			F_MEM|F_LOAD|F_DISP,
	DGPR(RT), DNA,		DNA, DGPR(BS), DNA,
	(ss_lr_temp = READ_WORD(WR_BASE(GPR(BS) + OFS)),
	 SET_GPR(RT, ((GPR(RT) & ~WR_PROT_MASK1(GPR(BS) + OFS)) |
		      ((ss_lr_temp >> (8 * (4 - WR_SIZE(GPR(BS) + OFS)))) 
		       & WR_PROT_MASK1(GPR(BS) + OFS))))))
#endif

#define SB_IMPL								\
  {									\
    byte_t _src;							\
    enum md_fault_type _fault;						\
									\
    _src = (byte_t)(word_t)GPR(RT);					\
    WRITE_BYTE(_src, GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SB, 			0x30, 
	"sb", 			"t,o(b)",
	WrPort, 		F_MEM|F_STORE|F_DISP,
	DNA, DNA,	 	DGPR(RT), DGPR(BS), DNA)

#define SH_IMPL								\
  {									\
    half_t _src;							\
    enum md_fault_type _fault;						\
									\
    _src = (half_t)(word_t)GPR(RT);					\
    WRITE_HALF(_src, GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SH, 			0x32, 
	"sh", 			"t,o(b)",
	WrPort, 		F_MEM|F_STORE|F_DISP,
	DNA, DNA,	 	DGPR(RT), DGPR(BS), DNA)

#define SW_IMPL								\
  {									\
    word_t _src;							\
    enum md_fault_type _fault;						\
									\
    _src = (word_t)GPR(RT);						\
    WRITE_WORD(_src, GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SW, 			0x34, 
	"sw", 			"t,o(b)",
	WrPort, 		F_MEM|F_STORE|F_DISP,
	DNA, DNA,	 	DGPR(RT), DGPR(BS), DNA)

/* FIXME: this code not fault-safe, yet... */
#define DSW_IMPL							\
  {									\
    enum md_fault_type _fault;						\
									\
    if ((RT) & 01)							\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    WRITE_WORD(GPR(RT), GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    WRITE_WORD(GPR((RT) + 1), GPR(BS) + OFS + 4, _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(DSW,			0x35,
	"dsw",			"t,o(b)",
	WrPort,			F_MEM|F_STORE|F_DISP,
	DNA, DNA,		DGPR_D(RT), DGPR(BS), DNA)

/* FIXME: this code not fault-safe, yet... */
#define DSZ_IMPL							\
  {									\
    enum md_fault_type _fault;						\
									\
    WRITE_WORD(GPR(0), GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    WRITE_WORD(GPR(0), GPR(BS) + OFS + 4, _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(DSZ,			0x38,
	"dsz",			"o(b)",
	WrPort,			F_MEM|F_STORE|F_DISP,
	DNA, DNA,		DNA, DGPR(BS), DNA)

#define S_S_IMPL							\
  {									\
    enum md_fault_type _fault;						\
									\
    WRITE_WORD(FPR_L(FT), GPR(BS) + OFS, _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(S_S, 			0x36, 
	"s.s", 			"T,o(b)",
	WrPort, 		F_MEM|F_STORE|F_DISP,
	DNA, DNA,		DFPR_L(FT), DGPR(BS), DNA)

/* FIXME: this code not fault-safe, yet... */
#define S_D_IMPL							\
  {									\
    enum md_fault_type _fault;						\
									\
    if ((FT) & 01)							\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    WRITE_WORD(FPR_L(FT), GPR(BS) + OFS, _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    WRITE_WORD(FPR_L((FT)+1), GPR(BS) + OFS + 4, _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(S_D,			0x37,
	"s.d",			"T,o(b)",
	WrPort,			F_MEM|F_STORE|F_DISP,
	DNA, DNA,		DFPR_D(FT), DGPR(BS), DNA)

#if (!defined(MD_CROSS_ENDIAN) && defined(BYTES_BIG_ENDIAN)) || (defined(MD_CROSS_ENDIAN) && defined(BYTES_LITTLE_ENDIAN))
#define SWL_IMPL							\
  {									\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    _lr_temp = READ_WORD(WL_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    _lr_temp = (((GPR(RT) >> (8 * WL_SIZE(GPR(BS) + OFS)))		\
		 & WL_PROT_MASK2(GPR(BS) + OFS))			\
		| (_lr_temp & ~WL_PROT_MASK2(GPR(BS) + OFS)));		\
    WRITE_WORD(_lr_temp, WL_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SWL,			0x39,
        "swl",			"t,o(b)",
        WrPort,			F_MEM|F_STORE|F_DISP,
        DNA, DNA,		DGPR(RT), DGPR(BS), DNA)

#define SWR_IMPL							\
  {									\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    _lr_temp = READ_WORD(WR_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    _lr_temp = (((GPR(RT) << (8 * (4 - WR_SIZE(GPR(BS) + OFS))))	\
		 & ~WR_PROT_MASK2(GPR(BS) + OFS))			\
		| (_lr_temp & WR_PROT_MASK2(GPR(BS) + OFS)));		\
    WRITE_WORD(_lr_temp, WR_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SWR,			0x3a,
        "swr",			"t,o(b)",
        WrPort,			F_MEM|F_STORE|F_DISP,
        DNA, DNA,		DGPR(RT), DGPR(BS), DNA)
#else /* BYTES_LITTLE_ENDIAN */
#define SWL_IMPL							\
  {									\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    _lr_temp = READ_WORD(WL_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    _lr_temp = (((GPR(RT) >> (8 * (4 - WR_SIZE(GPR(BS) + OFS))))	\
		 & WR_PROT_MASK2(GPR(BS) + OFS))			\
		| (_lr_temp & ~WR_PROT_MASK2(GPR(BS) + OFS)));		\
    WRITE_WORD(_lr_temp, WL_BASE(GPR(BS)+OFS), _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SWL,			0x39,
        "swl",			"t,o(b)",
        WrPort,			F_MEM|F_STORE|F_DISP,
        DNA, DNA,		DGPR(RT), DGPR(BS), DNA)

#define SWR_IMPL							\
  {									\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    _lr_temp = READ_WORD(WR_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    _lr_temp = (((GPR(RT) << (8 * (4 - WL_SIZE(GPR(BS) + OFS))))	\
		   & ~WL_PROT_MASK1(GPR(BS) + OFS))			\
		  | (_lr_temp & WL_PROT_MASK1(GPR(BS) + OFS)));		\
    WRITE_WORD(_lr_temp, WR_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SWR,			0x3a,
        "swr",			"t,o(b)",
        WrPort,			F_MEM|F_STORE|F_DISP,
        DNA, DNA,		DGPR(RT), DGPR(BS), DNA)
#endif

#if 0
#define SWL_IMPL							\
  {									\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    _lr_temp = READ_WORD(WL_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    _lr_temp = ((GPR(RT) & ~WL_PROT_MASK(GPR(BS) + OFS)) |		\
                       (_lr_temp & WL_PROT_MASK(GPR(BS) + OFS)));	\
    WRITE_WORD(_lr_temp, WL_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SWL,			0x39,
	"swl",			"t,o(b)",
	WrPort,			F_MEM|F_STORE|F_DISP,
	DNA, DNA,		DGPR(RT), DGPR(BS), DNA)
/* #else */
DEFINST(SWL,			0x39,
	"swl",			"t,o(b)",
	WrPort,			F_MEM|F_STORE|F_DISP,
	DNA, DNA,		DGPR(RT), DGPR(BS), DNA,
	(ss_lr_temp = READ_WORD(WL_BASE(GPR(BS) + OFS)),
	 ss_lr_temp = (((GPR(RT) >> (8 * WL_SIZE(GPR(BS) + OFS))) 
			& WL_PROT_MASK2(GPR(BS) + OFS)) |
		       (ss_lr_temp & ~WL_PROT_MASK2(GPR(BS) + OFS))),
	 WRITE_WORD(ss_lr_temp, WL_BASE(GPR(BS) + OFS))))
#endif

#if 0
#define SWR_IMPL							\
  {									\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    _lr_temp = READ_WORD(WR_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    _lr_temp = ((GPR(RT) & ~WR_PROT_MASK(GPR(BS) + OFS)) |		\
                       (_lr_temp & WR_PROT_MASK(GPR(BS) + OFS)));	\
    WRITE_WORD(_lr_temp, WR_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SWR,			0x3a,
	"swr",			"t,o(b)",
	WrPort,			F_MEM|F_STORE|F_DISP,
	DNA, DNA,		DGPR(RT), DGPR(BS), DNA)
/* #else */
DEFINST(SWR,			0x3a,
	"swr",			"t,o(b)",
	WrPort,			F_MEM|F_STORE|F_DISP,
	DNA, DNA,		DGPR(RT), DGPR(BS), DNA,
	(ss_lr_temp = READ_WORD(WR_BASE(GPR(BS)+OFS)),
	 ss_lr_temp = (((GPR(RT) << (8 * (4 - WR_SIZE(GPR(BS) + OFS)))) 
			& ~WR_PROT_MASK2(GPR(BS)+OFS)) |
		       (ss_lr_temp & WR_PROT_MASK2(GPR(BS)+OFS))),
	 WRITE_WORD(ss_lr_temp, WR_BASE(GPR(BS)+OFS))))
#endif

/* reg+reg loads and stores */

#define LB_RR_IMPL							\