pll.tan.rpt

用以实现信号的任意分频

; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[16] ; count[20] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[17] ; count[20] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[19] ; count[20] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[18] ; count[20] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[21] ; count[20] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[0]  ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[1]  ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[31] ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[3]  ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[2]  ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[4]  ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[5]  ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[6]  ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[7]  ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[8]  ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[9]  ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[10] ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[11] ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[12] ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[13] ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[14] ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[15] ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[16] ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[17] ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[19] ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 86.21 MHz ( period = 11.600 ns )                    ; count[18] ; count[21] ; clk        ; clk      ; None                        ; None                      ; 7.600 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;           ;           ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+----------+-----+------------+
; Slack ; Required tco ; Actual tco ; From     ; To  ; From Clock ;
+-------+--------------+------------+----------+-----+------------+
; N/A   ; None         ; 5.000 ns   ; div~reg0 ; div ; clk        ;
+-------+--------------+------------+----------+-----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed Apr 23 12:57:39 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pll -c pll
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 66.67 MHz between source register "count[0]" and destination register "count[14]" (period= 15.0 ns)
    Info: + Longest register to register delay is 11.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC45; Fanout = 161; REG Node = 'count[0]'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = SEXP5; Fanout = 1; COMB Node = 'count~709'
        Info: 3: + IC(0.000 ns) + CELL(5.000 ns) = 11.000 ns; Loc. = LC12; Fanout = 137; REG Node = 'count[14]'
        Info: Total cell delay = 10.000 ns ( 90.91 % )
        Info: Total interconnect delay = 1.000 ns ( 9.09 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_43; Fanout = 33; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC12; Fanout = 137; REG Node = 'count[14]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_43; Fanout = 33; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC45; Fanout = 161; REG Node = 'count[0]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Micro setup delay of destination is 2.000 ns
Info: tco from clock "clk" to destination pin "div" through register "div~reg0" is 5.000 ns
    Info: + Longest clock path from clock "clk" to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_43; Fanout = 33; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC11; Fanout = 1; REG Node = 'div~reg0'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Longest register to pin delay is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC11; Fanout = 1; REG Node = 'div~reg0'
        Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'div'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 109 megabytes of memory during processing
    Info: Processing ended: Wed Apr 23 12:57:40 2008
    Info: Elapsed time: 00:00:01