asyn_fifo_distrib_64.edn

用FPGA来实现摄像头的捕捉和采集

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2002 3 8 1 37 37)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 4.1i"))))
   (comment "This file is owned and controlled by Xilinx and must be used
solely for design, simulation, implementation and creation of design files
limited to Xilinx devices or technologies. Use with non-Xilinx devices or
technologies is expressly prohibited and immediately terminates your license.
Xilinx products are not intended for use in life support appliances, devices,
or systems. Use in such applications are expressly prohibited.
Copyright (C) 2001, Xilinx, Inc.  All Rights Reserved.")
   (comment "Core parameters: ")
       (comment "c_use_blockmem = 0 ")
       (comment "c_rd_count_width = 4 ")
       (comment "c_has_wr_ack = 0 ")
       (comment "c_has_almost_full = 1 ")
       (comment "c_has_wr_err = 0 ")
       (comment "c_wr_err_low = 0 ")
       (comment "c_wr_ack_low = 0 ")
       (comment "c_data_width = 16 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_rd_err_low = 0 ")
       (comment "c_rd_ack_low = 0 ")
       (comment "c_wr_count_width = 4 ")
       (comment "InstanceName = asyn_fifo_distrib_64 ")
       (comment "c_has_rd_count = 1 ")
       (comment "c_has_almost_empty = 1 ")
       (comment "c_has_rd_ack = 0 ")
       (comment "c_has_wr_count = 1 ")
       (comment "c_fifo_depth = 63 ")
       (comment "c_has_rd_err = 0 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell FDCE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port CLR (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell FDE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell FDPE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port PRE (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell LUT4 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port I3 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell MUXCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port DI (direction INPUT))
                   (port CI (direction INPUT))
                   (port S (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell MUXCY_D (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port DI (direction INPUT))
                   (port CI (direction INPUT))
                   (port S (direction INPUT))
                   (port O (direction OUTPUT))
                   (port LO (direction OUTPUT))
               )
           )
       )
       (cell MUXCY_L (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port DI (direction INPUT))
                   (port CI (direction INPUT))
                   (port S (direction INPUT))
                   (port LO (direction OUTPUT))
               )
           )
       )
       (cell MUXF5 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port S (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell RAM16X1D (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port WE (direction INPUT))
                   (port WCLK (direction INPUT))
                   (port A0 (direction INPUT))
                   (port A1 (direction INPUT))
                   (port A2 (direction INPUT))
                   (port A3 (direction INPUT))
                   (port DPRA0 (direction INPUT))
                   (port DPRA1 (direction INPUT))
                   (port DPRA2 (direction INPUT))
                   (port DPRA3 (direction INPUT))
                   (port SPO (direction OUTPUT))
                   (port DPO (direction OUTPUT))
               )
           )
       )
       (cell XORCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port LI (direction INPUT))
                   (port CI (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell asyn_fifo_distrib_64
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename din_15_ "din(15)") (direction INPUT))
   (port ( rename din_14_ "din(14)") (direction INPUT))
   (port ( rename din_13_ "din(13)") (direction INPUT))
   (port ( rename din_12_ "din(12)") (direction INPUT))
   (port ( rename din_11_ "din(11)") (direction INPUT))
   (port ( rename din_10_ "din(10)") (direction INPUT))
   (port ( rename din_9_ "din(9)") (direction INPUT))
   (port ( rename din_8_ "din(8)") (direction INPUT))
   (port ( rename din_7_ "din(7)") (direction INPUT))
   (port ( rename din_6_ "din(6)") (direction INPUT))
   (port ( rename din_5_ "din(5)") (direction INPUT))
   (port ( rename din_4_ "din(4)") (direction INPUT))
   (port ( rename din_3_ "din(3)") (direction INPUT))
   (port ( rename din_2_ "din(2)") (direction INPUT))
   (port ( rename din_1_ "din(1)") (direction INPUT))
   (port ( rename din_0_ "din(0)") (direction INPUT))
   (port ( rename wr_en "wr_en") (direction INPUT))
   (port ( rename wr_clk "wr_clk") (direction INPUT))
   (port ( rename rd_en "rd_en") (direction INPUT))
   (port ( rename rd_clk "rd_clk") (direction INPUT))
   (port ( rename ainit "ainit") (direction INPUT))
   (port ( rename dout_15_ "dout(15)") (direction OUTPUT))
   (port ( rename dout_14_ "dout(14)") (direction OUTPUT))
   (port ( rename dout_13_ "dout(13)") (direction OUTPUT))
   (port ( rename dout_12_ "dout(12)") (direction OUTPUT))
   (port ( rename dout_11_ "dout(11)") (direction OUTPUT))
   (port ( rename dout_10_ "dout(10)") (direction OUTPUT))
   (port ( rename dout_9_ "dout(9)") (direction OUTPUT))
   (port ( rename dout_8_ "dout(8)") (direction OUTPUT))
   (port ( rename dout_7_ "dout(7)") (direction OUTPUT))
   (port ( rename dout_6_ "dout(6)") (direction OUTPUT))
   (port ( rename dout_5_ "dout(5)") (direction OUTPUT))
   (port ( rename dout_4_ "dout(4)") (direction OUTPUT))
   (port ( rename dout_3_ "dout(3)") (direction OUTPUT))
   (port ( rename dout_2_ "dout(2)") (direction OUTPUT))
   (port ( rename dout_1_ "dout(1)") (direction OUTPUT))
   (port ( rename dout_0_ "dout(0)") (direction OUTPUT))
   (port ( rename full "full") (direction OUTPUT))
   (port ( rename empty "empty") (direction OUTPUT))
   (port ( rename almost_full "almost_full") (direction OUTPUT))
   (port ( rename almost_empty "almost_empty") (direction OUTPUT))
   (port ( rename wr_count_3_ "wr_count(3)") (direction OUTPUT))
   (port ( rename wr_count_2_ "wr_count(2)") (direction OUTPUT))
   (port ( rename wr_count_1_ "wr_count(1)") (direction OUTPUT))
   (port ( rename wr_count_0_ "wr_count(0)") (direction OUTPUT))
   (port ( rename rd_count_3_ "rd_count(3)") (direction OUTPUT))
   (port ( rename rd_count_2_ "rd_count(2)") (direction OUTPUT))
   (port ( rename rd_count_1_ "rd_count(1)") (direction OUTPUT))
   (port ( rename rd_count_0_ "rd_count(0)") (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU0
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU1
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU2
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU3
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU4
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU5
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU6
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU7
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU8
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU9
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU10
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU11
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU12
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU13
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU14
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU15
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU16
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU17
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU18
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU19
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU20
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU21
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU22
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU23
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU24
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU25
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU26
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU27
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU28
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU29
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU30
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU31
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU32
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU33
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU34
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU35
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU36
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU37
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU38
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU39
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU40
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU41
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU42
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU43
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU44
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU45
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU46
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU47
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU48
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )